搜索资源列表
RISC-CPU
- 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。 程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC
cpu
- MIPS流水线CPU的工作原理和设计方法-The design and implementation of the pipelined CPU
cpu
- 这是本人的课程设计。采用微程序控制的CPU，能够从RAM中读取指令，并执行。包含MBR,MAR,IR,BR,ALU,PC等功能部件，能实现加减乘法，逻辑左右移位，逻辑与或非，在此基础上还可以拓展。希望能帮助你们。-This is my curriculum design. Micro-program control CPU can read instructions from the RAM and executed. Contains the MBR, MAR, IR, BR, ALU, PC
cpu
- 简易cpu 课程设计 vhdl modelsim-Easy cpu curriculum design vhdl modelsim
MIPS
- 基于32位字长的MIPS cpu设计的代码实现,包括指令和寄存器数据-Based on a 32-bit word length MIPS cpu design code, including instructions and register data
sim
- 8位的CPU设计，4条非R型指令，4条R型指令-CPU design of 8 bit, 4 non R type instruction, 4 R type instruction
CPU
- 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
simpleCpu
- relative cpu design implementation
Chapter-13
- 13.2 RISC-CPU设计 13.3 RISC-CPU Testbench设计-13.2 RISC-CPU design 13.3 RISC-CPU Testbench Design
CPU_design_report
- CPU设计与实践实验报告 70多页，详细说明各模块工作原理-cpu design report
Introduction-to-32bit-CPU
- 本课件介绍了如何设计32位CPU，设计过程和结构原理的讲解。-A brief introduction to the design of 32bits CPU.
logic-design-of-CPU
- 本文献介绍了基于32位架构的双发射流水线设计。-design of 32bits CPU
TCAM_2
- 经典RISC CPU 设计，和PCI8位指令单片机兼容，值得初学者看一下-Classic RISC CPU design, and PCI8 bit microcontroller compatible instruction, it is worth a look for beginners
multi-CPU
- 多时钟CPU设计，spartan 3e板上试验通过，支持部分mips指令，内含示例mips代码及二进制文件-Multiple CPU clock design, spartan 3e board test passed, support some mips instruction, containing sample code and binary files mips
single-CPU
- 单时钟CPU设计，spartan 3e板上试验通过，支持部分mips指令，内含示例mips代码及二进制文件-Single CPU clock design, spartan 3e board test passed, support some mips instruction, containing sample code and binary files mips
cheng
- 开放式实验，CPU的设计，乘法器实验，简单乘法器-Open experiment, CPU design, the multiplier experiment, a simple multiplier
CPU
- 设计一段程序来模拟优先级调度算法和时间片轮转算法。可以指定进程的数量、各进程需要CPU的时间和各进程的优先级。-Design a program to simulate the priority scheduling algorithm and the time slice rotation algorithm. You can specify the process of quantity, the process requires CPU time and the process prior
electronic-clock-design
- 基于单片ＣＰＵ的ＬＣＤ显示电子时钟设计C++源代码超精准。-Ultra-precise chip CPU, LCD display electronic clock design C++ source code.
EDAandVHDL3
- 包含本系列的第三部分内容，详细介绍了VHDL状态机的概念及其使用和16位CISC CPU设计。-The third part contains the contents of this series, detailing the concept and its use of 16-bit CISC CPU design and VHDL state machine.
OpenMIPS_VerilogHDL_Study_v1.1
- 10天用verilog实现MIPS_cpu，内有清晰结构图。很好的cpu设计学习资料！-10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!