搜索资源列表
FMCOS
- 资料的详细功能、包含内容 复旦的i-cpu cos design
add32
- 由1位加法器级联得到的32位加法器 是设计单周期cpu的时候的基本部件-use 1 adders to be a 32 adder it is necessary for you to design a cpu
gpr
- 32个寄存器组成的寄存器堆 用于在cpu设计中存储数据-made up of 32 regs be used to design single cpu
110104010104
- 解决的主要问题 （1）MFC界面设计 （2）模拟生产者消费者的互斥操作 （3）各信号量及互斥体的使用 线程 线程是程序独立运行的基本单位，一个程序通过执行多个线程可以提高机器本身资源的利用率，同时也可以完成多任务并行运行的操作，多线程可以实现并行处理，避免了某项任务长时间占用CPU时间。 互斥体 互斥体与临界区很相似，但是使用时相对复杂一些，它不仅可以在同一应用程序的线程间实现同步，还可以在不同的进程间实现同步，从而实现资源的安全共享。 信号量 信号量是一个
risc8_cpu_verilog
- 该实例设计的RSIC-CPU总线结构采用数据线（8位）和指令线（12位）独立分离的哈弗结构，把存储寄存器RAM当做寄存器来寻址使用以方便编程。-The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as
8bit_CPU
- 用logisim设计的8位精简指令集cpu，有需要的话以后会开发编译器。-Using logisim design of the 8 bit reduced instruction set CPU, there is a need to develop after the compile
SimpleCPU
- 分别对运算器、寄存器组以及控制器进行设计，最后将其组合为一个简单的8位CPU，并能够加载测试程序进行测试-Respectively, calculator, and a controller register set design, and finally combined into a simple 8-bit CPU, and able to load test program
dsp28335-sch-pcb-kai-fa-ban-2
- 自己画的dsp 28335的cpu核心板，给单位的自动化产品检测台使用，在在使用中大放异彩，dsp软件采用matlab模型设计 我只用了1天的时间完成了大概半个月的工作量，非常好赶紧下载吧。-His paintings DSP 28335 CPU core board, for automation product testing station units, in shine in use, DSP software using MATLAB model design I use the 1
DigitalCompinacijaSimulacija
- It is a bridge between CPU and sensors where user can not connect sensors directly on CPU. It consumes very small number od LUTs and it is suitable for CPLD design. it works on following way, when logic detects falling edge of RX, then this action tr
cpu110
- 基本功能的cpu，自定义内存内容~了解CPU运作原理~-design of cpu,VHDL environment~
JCHENG2
- 设计一个程序模拟进程管理的过程,采用时间片轮转法，进程占用CPU的时间片有每个进程的优先数来确定。(约定：每个优先数对应10分钟)-design a simulation process management process using time-Web, the process of CPU time for each and every piece of the process to determine the priority number. (Agreement : each corre
cpu110
- 基本功能的cpu，自定义内存内容~了解CPU运作原理~-design of cpu,VHDL environment~
JCHENG2
- 设计一个程序模拟进程管理的过程,采用时间片轮转法，进程占用CPU的时间片有每个进程的优先数来确定。(约定：每个优先数对应10分钟)-design a simulation process management process using time-Web, the process of CPU time for each and every piece of the process to determine the priority number. (Agreement : each corre
my_cpu
- 计算机组成原理实验代码：单周期Cpu设计，附上检测指令， 在ISE 14.4通过检测-Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4
syn_wr
- 一般来说，CPU的读写时钟会引入到PLD中，笔者利用CPU的读写时钟实现同步读写寄存器，提高设计的可靠性。因此这种建模方式是推荐的CPU读写PLD寄存器建模方式-In general, CPU clock reading and writing will be introduced to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve d
CPU_design_Example
- 设计的CPU字长为16位，可以实现子程序调用，分支，循环及各种算术逻辑运算等功能。 访存的指令采用寄存器间址寻址(R)或是基址寻址X(R)实现， -Design CPU 16 word length can be achieved subroutine calls, branches, loops, and various arithmetic and logical operations and other functions. Between instruction fetch re
singleTcpu
- 单周期cpu设计，基于xilinx ISE环境设计，使用MIPS语言-Single cycle, the CPU is designed, based on xilinx ISE environment design, the use of MIPS language
NeonLightPLC
- PLC类型：西门子cpu224xp 题目：霓虹灯广告屏装置的PLC系统设计 -the design for neon light with PLC(simens cpu 224xp and two EM222-8DO)
VHDL
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
yu
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design