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DivFrec
- Employ IP cores in VHDL to describe some functions Module digital clock manager , in this case to create a frequency divider
jquerybeforeafter
- jquery与HTML5实现拖动图片变换效果,拖动中间的分隔线,可看到两种截然不同的效果,一边是清淅的图像,一边是模糊的图片,当然是调用了两张分别处理过的图片,综合运用jquery.beforeafter-1.3.js,jquery-ui-1.8.13.custom.min.js,jquery-1.6.1.min.js等jquery插件来实现,在图片中你可看到模特的脸,左边是不清淅的,右边则是高清的,你可通过中间的分隔条来向左或向右拖动查看。 因为用了HTML5技术,所以测试时候IE8
clk-ls1x
- imx integer fixup divider clock for Linux v2.13.6.
irq_nmi_defs_asm
- mxs fractional divider clock for Linux v2.13.6.
clkt34xx_dpll3m2
- OMAP34xx M2 divider clock code.
traffic_light_3_09
- 数码管驱动、HC595驱动、VHDL、分频器-Digital tube drive, HC595 drive, VHDL, divider
myproj
- 1) 可以产生四种波形:正弦波,方波,三角波,锯齿波。 2) 实现分频可调,分频比从2~256可调,通过两个按键进行+1和-1的调整。 3) 信号幅度可调,幅度增益从1~4倍可调,过两个按键进行+1和-1的调整。 4) 8位数码管的前3位显示分频比,最后一位显示幅度增益,中间的四位分别代表四种波形是否输出,若输出则显示’1’,否则显示’0’。 5) 可实现四种波形的叠加,当有两种波形叠加时,增益不能超过3,当是四种或三种波形叠加时,增益只能为1. -1) can produc
fp_prj
- 分频器,Verilog语音编写,quartus仿真过,可以利用使蜂鸣器发生-Frequency divider, Verilog speech writing, quartus simulation, can make use of the buzzer
Lab1~3
- 此為VHDL之暫存器、栓鎖器、三態匣、計數與除頻電路以及時脈產生電路-This is a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit
cymometer
- 硬件频率计的实现,包括十分频,门控信号产生,频率测量等-cymometer implementation, involving 10 times divider, generating gate controling signal and frequency measurement
second
- 利用Verilog HDL语言进行数字系统设计实现秒表的设计,涵盖原理图设计、文本设计以及进行波形仿真,并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
counter
- 一个100MHZ的时钟信号经过分频器得到1HZ信号,然后输入到三位计数器中,计数器的输出在相应的FPGA上的LED灯上展示。该程序主要包含四部分:测试文件、顶层文件、分屏器模块和计数器模块。-100MHZ clock signal through a divider to get 1HZ signal, and then input to the three counters, the output of the counter displayed on the corresponding LE
LIBRARY-IEEE
- 将1Mhz的频率信号转换成29hz的频率。分频器-Converting the frequency signal into a frequency of 29hz of 1Mhz. Divider
soda
- 实现一个苏打可乐售卖机,包括时钟分频,自动找零,能否售卖成功等功能。是中山大学移动信息工程学院数字设计的基础练习之一。-Achieve a Coke vending machine soda, including the clock divider, automatic change, the ability to sell successfully, and other functions. Exercise is one of the basic movement of Informatio
shuzizhong
- 秒计数器,分计数器,时计数器,分频器,数字钟实验-Second counter, minute counter, counter, divider, digital clock experiment
Microsoft-Word--(11)
- 分频器程序,可以实现分频器的功能,很方便的使用可以实现分频器-Divider program, you can achieve divider function, it is convenient to use the divider can be achieved
ex1_clkdiv
- Verilog语言编写,通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
plj
- 时钟分频器原理与实现,计数跳变的频率和加减模式可实时变化,通过Nano实验板上的LCD显示器显示。计数频率、加减选择和初始化操作通过板上的拨动开关和Reset按钮实现。-Principle and Implementation clock divider, counting and addition and subtraction frequency hopping mode changes in real time, through the LCD display panel show Nan
clk-divider
- Frontend part of the Linux driver for the Afatech 9005 USB1.1 DVB-T receiver.
fixed_pointDivider
- 关于定点除法的VHD实现,找了好久,奉献出来大家一起学习!-fixed_point divider is implemented in FPGA .