搜索资源列表
frequency-divider
- 利用FPGA实现分频器功能并完成LED数码管静态和动态显示-Using FPGA to achieve crossover features and complete LED digital control static and dynamic display
i2c-designware
- Provides clock implementations for three different types of clock devices on the Axxia device: PLL clock, a clock divider and a clock mux.
irq_impl
- clk register fractional divider for Linux v2.13.6.
imx6qdl-wandboard-revb1
- DOC: basic fixed multiplier and divider clock that cannot gate.
io_ordering
- DPLL rate rounding: minimum DPLL multiplier, divider values.
diviseur
- it s descr iption in VHDL code of divider. this is complex arithmetic operation
sja1000
- clock divider register.
cpld
- CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des
fenpin
- 通过FPGA设计实现的分频模块，仿真可以通过，适合初学者学习。-Through the FPGA design of frequency divider module, simulation can be passed, for beginners to learn.
frequency-demultiplier
- 电子分频器：有源电路，位于功率放大器之前，将前置音频信号分频后再用各自独立的功率放大器，把每一个音频频段信号给予放大，然后分别送到相应的扬声器单元-Electronic frequency divider: active circuits, in front of the power amplifier, will lead audio signal frequency and then separate the power amplifier, the every audio frequenc
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language
my_32fp_mult
- 这是一个计算32位浮点数的除法器，ALTERA的FPGA可直接用，用VHDL语言写的，希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
fenpin
- 对m序列进行2ASK调制 包含分频器 m序列发生器 正弦信号发生器 二路选择器4个模块-process m sequence with 2Ask includes frequency divider, m sequence generator, sine signal generator and MUX
st-clkgen-prediv
- Binding for a ST pre-divider clock driver.
mm_internal
- Binding for a ST divider and multiplexer clock driver.
clk_div
- Clock divider in VHDL.
sonixb
- high-nibble is sensor clock divider, changes exposure on sensors which use a clock generated by the bridge. Some sensors have their own clock.
jiaotongdneg
- 交通信号灯 本程序设计中用到了8253,8255，8259三个芯片。利用8253分频产生0.1S的时钟，8255连接LED灯输出，利用8259产生中断，控制交通灯的状态。-Traffic lights used in the design of this program 8253,8255,8259 three chips. The use of 8253-Divider 0.1S clock, LED light output 8255 connected by 8259 to gener
streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
myfpga
- 这个是经典的FPGA的相关的乘法器，除法器的代码，还有别的可用的资料，都是网络上攒的，并且真的是非常经典-This is a classic of the relevant multiplier divider FPGA code, as well as other available information, are saved on the network, and really is very classic