搜索资源列表
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
compare
- 八位字节比较器，四选一多路选择器，二分频电路-Octet comparator 4 election more than one way selector, the second divider circuit
AnJian_1602
- 计算器设计。采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示在数码管上。计算部分为加法器、减法器、乘法器和除法器组成。使用Altera公司的QuartusII开发软件进行功能仿真并给出仿真波形，并下载到试验箱,用实验箱上的按键开关模拟输入，用数码管显示十进制计算结果。通过外部按键可以完成四位二进制数的加、减、乘、除四种运算功能，其结果简单，易于实现。-Calculator design. Using a field programmable logic d
qnr_verilog
- 量化取整QNR内部主要包括一个divider模块及产生数据输出有效和循环结果到最近整数的电路，包含仿真结果图。-Rounding quantization internal QNR includes a divider module and generates data output valid and circulating the results to the nearest integer circuit, including the simulation results shown in
skfp
- 数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，参考代码中的数控分频器是用可并行预置的加法计数器设计完成的，当加法计数器溢出时进行并行预置。-The function of NC divider is when in the input given different input data, the input clock signal has a different frequency ratio, reference code in the NC divi
eda-Electronic-organ
- 本设计的是简易电子琴的实现。采用EDA作为开发工具，VHDL语言为硬件描述语言，quartus II作为程序运行平台，所开发的程序通过调试运行、波形仿真验证，实现了设计目标。本程序使用的硬件描述语言VHDL，可以大大降低了硬件数字系统设计的入门级别。 利用数控分频器设计一个电子琴硬件电路，通过键盘输入使扬声器发出不同频率的声音。-This design is the realization of simple electronic piano. Using EDA a
FENPIN48
- FPGA分频器，利用计数器计数，将外部晶振的48MHZ时钟分频为1MHZ-48M frequency division 1M frequency divider
egprog
- EG8010 is a digital pure sine wave inverter ASIC (Application Specific Integrated Circuit) with complete function of built-in dead time control. It applies to DC-DC-AC two stage power converter system or DC-AC single stage low power frequency tra
Divide
- This a divider verilog code
clk_div
- 时钟分频功能模块，采用计数器后两位异或再移位的方式实现，节约资源。-Clock divider function module, after using two different counter or re-shift ways to save resources.
Clk50M_div_1HZ
- 分频实验，将50M时钟分频为1HZ，输出LED1，闪亮-Crossover experiment, 50M clock divider is 1HZ, output LED1, shiny
clk_divR
- frequency divider into reglable frequence
8051F340_HMC1033_HMC988_HMC987_SPI
- Keil uvision 的8051F340源码，可以遥控，SPI口控制HMC1033到550MHz时钟，HMC988分频器，HMC987八路扇出电路-Keil uvision of 8051F340 source, you can remote control, SPI port control HMC1033 to 550MHz clock, HMC988 divider, HMC987 eight fan-out circuit
divider
- 用VHDL程序实现数字电路里面的分频计数器的功能-Digital circuitry inside the program using VHDL-scale counter function
T2_DIV
- 对于学习分频器的VHDL学习有很大帮助，里面的资料挺好-Learning for learning VHDL divider helps a lot of very good inside information
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector
VHDL-Programming-Examples
- 分频器、译码器、编码器、计数器、状态机等基本的硬件描述语言代码-The basic hardware divider, decoders, encoders, counters, state machine descr iption language code
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
fenpin
- 通用整数分频器，可以分频占空比为1:1，也可以为任意占空比-General integer frequency divider, can divide frequency and duty ratio of 1:1, also can be for any duty ratio
diviseurFrquence50MhzTo1hz
- this file about frequency divider 50 MHz to 1 Hz used in 7-segment display