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SA-1100
- Purpose Definition of constants related to the StrongARM SA-1100 microprocessor (Advanced RISC Machine (ARM) architecture version 4). This file is based on the StrongARM SA-1100 data sheet version 2.2. -Purpose Definition of constants related to th
MTP4
- 高性能RISC CPU： • 仅需学习35条指令： - 除跳转指令外，所有指令均为单周期指令 • 工作速度: - 振荡器/ 时钟输入为DC-20 MHz - 指令周期为DC -High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Sp
sfdiv
- Linux PA-RISC Project.
sfmpy
- Linux PA-RISC Project.
encoder
- 设计一个简单的RISC体系结构处理器的多周期指令译码器，完成指定6条指令译码。-Design a simple RISC processor architecture multi-cycle instruction decoder decoding instructions to complete the assigned 6.
pr22167
- Derived PR22167, which failed on some RISC targets. The call to foo() has two successors, one normal and one exceptional, and both successors use &a[0] and x. Expressions involving &a[0] can be hoisted before the call but those involving x cannot.
VLSI_RISC_chip_disk
- 这是《大型RISC处理器》书中附带光盘的内容，希望有用吧-a disk
not1
- Originally X was an array. As it s automatic it s natural to expect RISC compiler to accomodate at least part of it in the register bank.
risc16f84_latest.tar
- iT IS A 16 bit RISC processor,,It is easily virtualizable and reconfigurable.It is implemented in FPGA.
ecpu
- It is a type of RISC processor..it is easily reconfigurable and virtualizable.it is implemented on FPGA
btcx-risc
- Block until a buffer comes unlocked. This doesn t stop it becoming locked again - you have to lock it yourself if you want to preserve its state. -Block until a buffer comes unlocked. This doesn t stop it becoming locked again - you have to lock i
eisa
- eisa.c - provide support for EISA adapters in PA-RISC machines.
riscacisc
- RISC 和CISC 是目前设计制造微处理器的两种典型技术，虽然它们都是试图在体系结构、操作运行、软件硬件、编译时间和运行时间等诸多因素中做出某种平衡，以求达到高效的目的-RISC and CISC is the design and manufacture of two typical microprocessor technology, although they are trying to make some kind of balance in the architecture, op
cpu3
- 简易CPU可执行8条简单指令,如：add,xor,and等-risc cpu
risc8_cpu_verilog
- 该实例设计的RSIC-CPU总线结构采用数据线（8位）和指令线（12位）独立分离的哈弗结构，把存储寄存器RAM当做寄存器来寻址使用以方便编程。-The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as
arm_command
- ARM（Advanced RISC Machines）是微处理器行业的一家知名企业。设计了大量高性能、廉价、耗能低的RISC处理器、相关技术及软件。1985年，第一个ARM原型在英国剑桥诞生。ARM公司的特点是只设计芯片，而不生产。ARM将其技术授权给世界上许多著名的半导体、软件和OEM厂商，每个厂商得到的都是一套独一无二的ARM相关技术及服务。利用这种合伙关系，ARM很快成为许多全球性RISC标准的缔造者。-ARM (RISC Machines Advanced) is a well-know
riscv-spec-v2.0
- The RISC-V Instruction Set Manual
cpu
- 一份精简指令cpu源代码，用verilog编写，已经通过仿真验证，可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
Risc128
- 128 bit RISC processor implementation in verilog
tms320c6678
- tms320c6678 主要介绍了c66x的芯片功能，端口、控制器，封装，存储空间分布等-TI’s KeyStone Multicore Architecture provides a high-performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. KeyStone is the first of its kind that provid