搜索资源列表
Verilog
- 实用的verilog编程经验，推荐初学者详细阅读，-Verilog programming practical experience, recommended for beginners to read in detail,
syndetect
- 帧同步检测，verilog代码 是同步保护的经典范例-frame detection, verilog code
SystemVerilog_2nd.pdf
- System Verilog 验证设计。主要讲如何编写测试用例。设计数字电路比较经典的教程。-System Verilog design verification. Mainly about how to write test cases. Digital circuit design more classic tutorial.
config_ad6636
- 用Verilog正确配置ad6636，，在ISE环境中正确编译与实现-Properly configured with the Verilog ad6636,, compiled in the ISE environment and realization of the right
dds
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件，-verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
aes_verilog
- A RTL verilog coding for the project AES, which is a cryptography based concepts
USB_kz
- 提供Cy7C68013 USB芯片开发源程序，由verilog编写-Cy7C68013 USB chip to provide the development of source code, prepared by the Verilog
SPI_interface.ZIP
- SPI接口代码，非常精简，verilog版本。-SPI interface code, very streamlined, verilog version.
2fsk_final
- 全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code
ldcp_verilog
- ldpc verilog 程序 做ldpc硬件实现的可以-ldpc verilog procedures do LDPC hardware implementation can
Div3
- 一个除3器的Verilog源码，用于视频解码器的熵解码部分。纯组合逻辑，大小和加法器差不多。-In addition to device a Verilog source code 3, the video decoder for entropy decoding part. Pure combinational logic, about the size and adder.
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
dft
- verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
ASK_modulator
- 振幅键控ASK的调制解调Verilog实现，带测试文件-ASK amplitude shift keying modulation and demodulation Verilog implementation, with the test file
H.264Decoder
- H.264解码器，用verilog写成，可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
fir_lms
- 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
SDRAM_CONTROLlER_Modelsim
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和文档-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
divider16
- 16位小数除法器verilog源码，可综合的，已经仿真过。-16bit fractional numeral divider verilog source
I2C
- Verilog 实现 IIC 源码,包括各个时序信号的详细描述-Verilog code for IIC