搜索资源列表
DE2_CCD_binary
- verilog DE2 binary image (form CCD to VGA) output
Log_Shifter_Gate_Level_Design
- Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
fcsr
- 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
multi16
- verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
105230308VerilogHDLcoding
- verilog的非常好的材料，是verilogHDL编码风格的总结。-Verilog s very good material is a summary of verilogHDL coding style.
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
armok01120613
- arm verilog的相关代码 仅仅供学习使用-arm verilog code only for the relevance of learning to use
Verilog_HDL
- Verilog HDL程序设计教程,以可综合的设计为重点，同时对仿真和模拟也作了深入阐述。全面介绍了verilog HdL 词法，语法。-Verilog HDL Programming Guide, to be designed as an integrated focus on simulation and simulation at the same time also made to describe further. Verilog HdL gave a comprehensive ac
DSP
- 从算法设计到硬线逻辑的实现：复杂数字逻辑系统的Verilog HDL设计技术和方法，结合DSP算法介绍verilog HdL 设计。-From algorithm design to achieve hard-wired logic: complex digital logic system Verilog HDL design techniques and methods, combined with DSP algorithm design verilog HdL introduced.
ARM7_verilog
- arm 7 verilog code used setup soc
dds
- 直接频率合成器，采用verilog hdl-Direct frequency synthesizer using verilog hdl
div16
- 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
fpgaPCI
- fpga开发pci的verilog，不可多得的源代码。-FPGA development pci of verilog, rare source code.
avalon_pwm_module_v2.51_completed
- 数字PWM的verilog描述，适合于数字控制的DC-DC-Digital PWM s Verilog descr iption, suitable for digital control of DC-DC
15NIOSIIclock
- nios num clock verilog code
Verilog_handbook
- Verilog_handbook classic Verilog book -Verilog_handbookclassic Verilog book
100Examples
- verilog 语言 可以免费下载的程序-Verilog language can be downloaded for free procedures
usb11.tar
- USB1.1 SOURCE CODE verilog