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ourdev_441156
- AVR单片机是1997年由ATMEL公司研发出的增强型内置Flash的RISC(Reduced Instruction Set CPU) 精简指令集高速8位单片机。AVR的单片机可以广泛应用于计算机外部设备、工业实时控制、仪器仪表、通讯设备、家用电器等各个领域。-AVR Microcontroller ATMEL Corporation in 1997 developed by the enhanced built-in Flash of the RISC (Reduced Instructio
cpu16
- 16位cpu设计vhdl源码。主要实现risc机器模型-16-bit cpu design code
Verilog-HDLTOP-DOWN
- 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元（CPU）的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.
sparc_verilog
- open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
simplesim-3v0e
- SimpleScalar 模拟器模拟的是一个超标量，5级流水的RISC体系结构的CPU模型，提供了从最简单到超标量乱序发射的不同的模拟程序。sim-outorder 是一个具有完整功能的模拟程序。在sim-outorder中使用了几乎所有的模拟资源，在阅读代码之前对模拟的体系结构和模拟资源充分的了解，能够大大提高下一步工作的效率。-SimpleScalar tool
smdk2413_application_note_rev10
- SMDK2413 (Samsung MCU Development Kit) for S3C2413X is a platform that is suitable for code development of SAMSUNG s S3C2413X 16/32-bit RISC microcontroller (ARM926EJ-S) for hand-held devices and general applications. The S3C2413X consists of 16-/32-
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
Code-Vision-AVR-C-11
- AVR 单片机的C语言例程 一共有30多个，基本通用-AVR RISC(Reduced Instruction Set CPU
arm-gcc-3.4.4-gm8180.tar.bz2
- GM’s GM8180 MDC1 hardware environment is a highly efficient RISC-based platform for the purpose of verifying and evaluating AMBA-based designs in the early development stage. The complete set of MDC1 GM8180 platform consists of a main board (MB12
RISC_CPU
- 1. RISC工作每执行一条指令需要八个时钟周期。RISC的复位和启动通过rst控制，rst高电平有效。Rst为低时，第一个fetch到达时CPU开始工作从Rom的000处开始读取指令，前三个周期用于读指令。 在对总线进行读取操作时，第3.5个周期处，存储器或端口地址就输出到地址总线上，第4--6个时钟周期，读信号rd有效，读取数据到总线，逻辑运算。第7个时钟周期，rd无效，第7.5个时钟地址输出PC地址，为下一个指令做好准备 对总线写操作时，在第3.5个时钟周期处，建立写的地址，第
risc_FPGA
- 使用ISE12.1开发的简单cpu基于RISC的！有测试代码。没有下载到板子上，通过了测试！有详细解释-ISE12.1 FPGA CPU RISC
Insiders_Guide_XC166
- The C166S V2 CPU core used in the XC166 seriesmakes extensive use of Reduced Instruction Set Computer (RISC) concepts to achieve its blend of very highperformance at modest cost.