搜索资源列表
DDR3_128M16bit_2Port64bit
- Xilinx spartan6 DDR3驱动,编程语言Verilog,基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
RAM
- 用verilog实现了IP核的使用,例化了一个RAM,用来进行读写操作,另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
pic10
- 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码,当然有一些模块是在quartus中直接编辑波形测试的,所以没有响应的测试脚本文件。 tri_state_port的测试还未完成,test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档: PIC10_RISC_Design.pdf:原文(verilog代码基本都来自原文,对一部分进行了改进),这篇文章写
Buf_FiFo
- verilog 编写的FIFO,里边有IP核和控制模块,-verilog write FIFO, inside the IP core and control module,
ROM
- FPGArom的IP核使用及仿真,Verilog语言,非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed
zhixinkeji
- 北京至芯科技FPGA的学习资料,从备战Quartus II安装到IIC通信协议,每一章都有Verilog代码并且可以实现仿真程序,非常好用,讲的很详细-Beijing Science and Technology FPGA to the core learning materials, preparing to install Quartus II IIC communication protocol, each chapter Verilog code and can achieve sim
ROM
- 使用verilog语言实现对altera下cycloneII系列FPGA的片上ROM的创建,读写,调用IP核-Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
dfe_filter
- DEF算法的FIR滤波器verilog代码,内有乘法器IP核,可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
MY 80c51 IP
- verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
modelsim se 10.1a crack
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段,是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation
高大上欧美风商务PPT模板
- JPEG_d IP Core Verilog crypted source
8051Core
- 8051 Core Verilog RTL IP Code
AD多通道采集 FFT实验
- FFT核和AD多通道采集的Verilog HDL(Verilog HDL with FFT Core and AD Multichannel Acquisition)
MIPI_CSI_2_Rx
- MIPI CSI 2 Rx verilog / vhdl core
MIPI_DSI_Tx
- MIPI DSI Tx verilog / vhdl core
异步FIFO
- 纯Verilog实现的异步FIFO,分为读写控制模块,SRAM CORE,同步等几个模块,内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)