搜索资源列表
ads7887
- 使用VerilogHDL语言实现ADS7887的时序功能。-Use VerilogHDL language ADS7887 timing function.
DS1302
- 基于VerilogHDL编写的时钟管理芯片DS1302实验开发程序。-VerilogHDL prepared based on clock management chips DS1302 experimental development program.
USB2_0
- USB2_0控制器CY7C68013与FPGA接口的VerilogHDL实现.rar-CY7C68013 and FPGA controller USB2_0 interface VerilogHDL achieve. Rar
AD9954_test
- AD公司DDS芯片AD9954的Verilog测试程序-VerilogHDL test program of DDS chip--AD9954 ,producted by AD company
CIC
- 积分梳妆滤波，介绍了积分梳状滤波器(CIC)设计，压缩包里面有程序的流程图，采用verilogHDL编写-jifenshuzhuanglubo
FFT
- OFDM系统中FFT的VerilogHDL语言实现-FFT of OFDM system VerilogHDL language
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
ep_rom
- 采用VerilogHdl语言编写的，介于FPGA的EPROM的开发读写-VerilogHdl the use of languages, ranging from the development of FPGA to read and write the EPROM
debounce_2_Verilog
- 用VerilogHDL编写的按键消抖程序 分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下后,产生时间为10ms的低电平信号,即LED亮10m-*Project Name :debounce *Module Name :debounce *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *Date : 2011-11-
fir
- verilogHDL编写的低通滤波器模块，在ISE软件中仿真过-verilogHDL prepared by low-pass filter module, in the ISE simulation software have been
lift-verilogHDL
- 利用verilog语言实现一个简单的电梯控制，可借助最小系统开发板进行试验-control lift by using verilong HDL
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序，可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA
CRC32
- 基于FPGA平台的用verilogHDL设计的CRC32模块-a code for CRC32 based on FPGA by verilogHDL
VERILOGHDL
- this a book about the verilog-hdl design and circuit simulation and synthesize example
VerilogHDL
- 王金明：《Verilog HDL 程序设计教程》程序-Wang Jinming:
t2b
- 温度码到二进制吗的转换的ｖｅｒｉｌｏｇＨＤＬ代码。-Temperature code to do the conversion of binary code verilogHDL.
arm10-behavioral
- arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ-arm10-behavioral simulation code of conduct verilogHDL
M_design
- 设计一个简单的8比特ALU和一个简单的存储器，是用VerilogHDL实现的，这是个题目及其解析-Design of a simple 8-bit ALU and a simple memory, is used VerilogHDL realized, this is a subject and its analytic
ALU_design
- 设计一个简单的8比特ALU的源代码，是用VerilogHDL实现的-Design of a simple 8-bit ALU s source code is achieved using VerilogHDL
ALU---M_design
- 设计一个简单存储器的源代码，是用VerilogHDL实现的-Design of a simple memory of the source code, is used to achieve VerilogHDL