搜索资源列表
ml605_PCIe_Gen1_x8_rdf0008_13.4_c
- 该压缩文件为一个pcie接口设计源程序，源程序包含一个8通道gen1的pcie IP CORE和相应的用户接口程序，烧到开发板ml605中测试通过。 -The compressed file is a pcie interface design source code, source code contains an 8-channel gen1 of pcie IP CORE and the corresponding user interface program, burn developm
r7lite
- R7Lite是基于Xilinx的Kintex7系列FPGA的PCI Express参考设计代码，PCIe 2.0 4x模式，包括了FPGA实现，Linux下驱动和测试例程。-R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing App
nysa_sata_latest.tar
- The Xilinx CORE Generator™ is used to create a single-lane PCIe Endpoint Plus design. The generated PCIe system contains the PCIe endpoint plus block, GTP tiles, block RAMs, and clock and reset modules. The tutorial below shows how to create the
design_pcie-based-on-FPGA
- the interface design of pcie based on FPGA
SV_AVMM_DMA_DDR3_128M
- altera公司avmm借口pcie dma设计实例，在实际工程中应用成功(Altera avmm, Inc., PCIe DMA design example, applied successfully in actual engineering)
virtex7_pcie_dma_latest.tar
- PCIE_dma 设计，基于xilinx virtex7 fpga芯片，实现高速传输(PCIE_dma design, based on the Xilinx virtex7 FPGA chip, to achieve high speed transmission)
功率可配置远距离无线路由器
- MTK/联发2×2双频无线局域网5.0GHz网卡芯片MT7612EN 该MT7612E是一个高度集成的单芯片，内置了一个2×2双频无线局域网的无线。它支持IEEE802.11ac的标准草案，并提供最高的PHY速率可达867Mbps，提供功能丰富的无线连接和可靠的吞吐量从一个扩展的距离。优化的射频架构和基带算法提供了卓越的性能和低功耗消费。(MTK/mediatek 2 x 2 MT7612EN 5.0 GHz dual-band wireless LAN card chip The MT76
基于FPGA的PCIe总线DMA控制器的设计与验证
- 基于FPGA的PCIe总线DMA控制器的设计与验证(Design and verification of PCIe bus DMA controller based on FPGA)