搜索资源列表
SDRAM_ctrl
- 基于DE2的SRAM驱动，带测试程序。用VHDL语言编写。-sdram drive
XAPP134_SDRAM_VHDL
- XAPP134 SDRAM VHDL design file
UART_DMA
- 实用串口与SDRAM控制接口VHDL语言程序代码-Utility serial port and SDRAM control interface VHDL language code
s16_sdram
- VHDL 语言如何写SDRAM的源代码，很详细的-VHDL for SDRAM
sdram_access
- sdram 控制器，VHDL程序源代码。-sdram controller,vhdl program
ddr2_sdram_latest[1].tar
- ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
SDRAM_control_design
- 一个SDRAM控制器的参考设计vhdl语言，包含了全部逻辑功能代码以及约束文件，包括一些综合布线后的文件和波形，有较高的参考价值。-A SDRAM controller reference design vhdl language contains all logic code as well as the constraints file, including files and waveform integrated wiring, there is a high reference val
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
sdramtest
- vhdl语言编写读写三星SDRAM程序，包含读写控制程序，地址转化程序，测试模块程序-vhdl language, reading and writing the Samsung SDRAM program, contains the read and write control procedures address conversion program, the test module program
Using_the_SDRAM_on_DE0_Board
- Using the SDRAM on Altera’s DE0 Board with VHDL Designs
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
SDRAM_Modelsim
- 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
ddr3
- VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.
ep2c8ptft
- EP2C8Q208 TFT LCD彩屏VHDL工程，含SDRAM、PLL等内容。-EP2C8Q208 TFT LCD color screen VHDL projects, including SDRAM, PLL and other content.
sdram_ctrl1
- 基于VHDL语言，实现了sdram控制器，已经过验证可用-design for sdram control
ddr_sdram
- 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造； 支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较
Datasheet_HY5PS1G431C(L)FP_HYNIX
- Datasheet_HY5PS1G431C(L)FP_HYNIX