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ti dsp5000序列
- ti dsp5000序列的介绍,挺有价值的,现在奉献给大家,希望对大家在工作中有用。-ti dsp5000 sequence, quite valuable, and the dedication to you now, we hope to work in useful.
伪随机序列的说明和源代码
- 可控m序列产生器我分成四个小模块来做,M,M1,M2,M3分别对应为:m序列产生器、控制器、码长选择器、码速率选择器。-controllable m-sequence generator, I divided into four small modules do, M, M1, M2, M3, respectively : m-sequence generator, controller, code-selector, code rate selector.
8051之序列傳輸簡介
- 8051序列傳輸簡介-8051 Series transmission brief
单片机M序列发生器
- 基于51单片机实现的M序列发生器(伪随机序列),在Keil编程环境下的源码
WinCE下获取SD卡序列号
- 在WinCE环境下,用来获取SD卡的序列号
读取18B20序列号并在12864上显示的C程序
- 读取18B20序列号并在12864上显示的C程序,已通过测试,绝对可用
用伪随机序列实现加密保护
- 本文讨论了用伪随机序列实现加密保护的原理,方法及可编程逻辑器件(pLD)实现的具体方法,在此基础上 介绍了一种基于FPGA的网络传输信道加密系统。 关键词 网络安全 伪随机序列 加密 FPGA
work.rar
- 上载的内容为随机信号处理的作业,具体是:其中W(t)为均值为零,方差为3的白噪声。 (1)产生若干组500个点长随机序列。 (2)找一个ARMA模型与(1)中的500个点匹配。 (3)在产生一个500个点长的随机序列校正。 ,Upload the contents of random signal processing operations, specifically: one of W (t) for the mean zero, variance of white noise for
mydesign.rar
- 基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具, 各模块采用Verilog HDL设计并封装,顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。 ,FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simu
C语言ADC12单通道和序列通道单次转换程序
- MSP430系列单片机实用C语言程序设计ADC12单通道和序列通道单次转换程序,MSP430 Microcontroller C Programming Language ADC12 utility and sequence single-channel single-conversion process
用LV获取机器CPU和硬盘序列号
- 用LV获取机器CPU和硬盘序列号,labview 8.6版本可以使用-Access to the machine with the LV CPU and hard drive serial number, labview 8.6 version can be used
m_vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器,采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值(程序中设定好四种非零初值可选)-m sequence vhdl
fpdpsk
- FSK/PSK信号调制器的VHDL程序,共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
Sequence-detector-design
- 序列检测器设计的思路大多都是用FSM来实现的,此思路是通过移位寄存器来实现序列检测-Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
DSSS-Transmitter
- 北斗定位系统卫星下行信号的基带处理部分——基于FPGA的直接序列扩频发射机的设计与仿真。-Beidou Positioning System satellite downlink of the baseband signal in part- based on direct sequence spread spectrum FPGA Design and Simulation of the transmitter.
c21_pn_code_generator
- 精通verilog HDL语言编程源码之7——伪随机序列应用设计-Proficient in programming language source verilog HDL of 7- the application of pseudo-random sequence design
xuliejiancesheji
- 用状态机实现一序列检测器,即检测到串行码{1110010}后,检测器输出1,否则输出0; -State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0
序列检测器
- 本例子为一个序列检测器的程序,序列为:11001001000010010100,检测的序列为10010(This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010)
11位巴克码序列峰值检测器
- (1)能够检测巴克码序列峰值; (2)在存在1bits错误情况下,能够检测巴克码序列峰值 (3)具体说明参见说明文档((1) the spike sequence of Barker code can be detected; (2) the spike sequence of Barker code can be detected under the condition of 1bits error)
110序列检测器
- 110的序列检测器,添加了使能端检查其正确性(The sequence detector of 110 adds the enable end to check its correctness.)