搜索资源列表
risc cpu
- 一个很好的16位cpu ip内核,用quartus写的
freerisc8_11.zip
- 8位RISC CPU的VERILOG编程 SOURCECODE,8 RISC CPU VERILOG programs SOURCECODE
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码(VERILOG 版)-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
CPU
- 八位简单risc cpu 设计的源代码,VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
OR1200_verilog
- or1200开源risc cpu的verilog描述实现,cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog descr iption of the risc cpu realize, cpu source code analysis and chip design source book
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
RISC
- hrisc cpu,为何只有vhdl选择呢?大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
32bit_RISC_CPU
- 32 risc cpu的参考设计,内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
risc
- 用Verilog 编写的8位risc cpu,行为级描述,可综合-6 bits risc cpu by Verilog
risc1200
- risc cpu设计源码,全部资料 欢迎下载-risc cpu core
alu
- this is source code in verilog for arithmatic logic unit for RISC cpu
RISCcpu
- this verilog model of RISC CPU-this is verilog model of RISC CPU
risc_cup
- 精简指令集CPU的VERILOG语言实现,很有用-RISC CPU the VERILOG language, very useful
32-bit-RISC-CPU-ARM
- 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM chip application and selection
RISC-CPU-ARM
- 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM chip application and selection
RISC-CPU-design
- 16位RISC-CPU设计,高四位为操作码,低12位为地址,寻址空间位4KB。包含12条指令(预设16条指令),3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the thre
RISC-CPU
- 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
RISC-CPU
- 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件,和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理,和数据流动!!! 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线,和地址总线。区分数据和地址。 5. 仔细调试,因为书中有很多小错误。 程序经过quartusii编译通过,另外经过modelsim仿真正确。-RISC
RISC-CPU
- 精简指令集 16位流水线CPU 可实现硬件模拟-16-bit pipelined RISC CPU hardware emulation can be achieved