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cpu的VERILOG描述
- RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL descr iption
cpld_bus
- CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
verilog hdl教程135例
- 浅显易懂的vrilogHDL的程序，可以帮助你迅速上手-Easy and simple VerilogHDL programs to help you to get to the language quickly.
8051IPcore，verilogHDL实现
- 用verilog写的很好的cpu core-using Verilog write a good cpu core
VerilogHDL
- Verilog HDL程序，对硬件开发有兴趣或需要的朋友赶快down下来-Verilog HDL procedures, the development of hardware are interested or needs a friend to see down quickly down
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
veriloghdl快速入门
- verilog hdl 快速入门,里面包含很多有用的硬件描述语言的程序-Verilog HDL Quick Start, which contains many useful hardware descr iption language procedures
cardPhone
- 卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能-card billing telephone circuits, verilogHDL prepared with the major simulate the real phone function
RISC Core_verilog
- RISC的指令VerilogHDL实现-RISC instructions to achieve VerilogHDL
crcDecode
- 比较完善的CRC编码VerilogHDL描述-more perfect descr iption of CRC coding VerilogHDL
PAOBIAO_V
- 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL descr iption
gatediscrip
- 各种门电路模型的VerilogHDL描述-various gates model of Verilog HDL descr iption
manydecoders_V
- 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL descr iption
VerilogHDLICdesign
- 精通VerilogHDL：IC设计核心技术实例详解-proficient VerilogHDL : IC design example explanation of the core technology
RSSI_contr
- VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage
VGA_2c5
- FPGA EP2C5 VGA 使用verilogHdl-VGA EP2C5 FPGA use verilogHdl
mod6_divide
- 用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
de_mux
- 一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
VerilogHDL解码DS18B20
- DS18B20解码代码，verilogHDL实现。