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wishbone_bus_protocol
- 是一份介绍wishbone总线非常好的资料，讲的很详细，希望对大家有帮助！-This is a very good introductory information about wishbone bus , speak in great detail, I hope it is a help to all of you!
wb_dma
- wishbone接口dma控制器，适合于构建soc系统，特别适用于视频开发-dma controller with wishbone interface，fitting for soc design，especially for video development.
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
ethmac_latest[1].tar
- 10M/100M 以太网mac，wishbone接口，可以直接使用-10M/100M Ethernet mac, wishbone interface, you can directly use
wb-ddr
- 基于Wishbone总线的DDR控制器. -A wraper of DDR controller for wishbone bus.
This_is_pci-wishbone_nuclear_and_16450_serial_port
- 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
ata_latest.tar
- The OCIDEC (OpenCores IDE Controller) is a WISHBONE rev.B2 compliant ATA/ATAPI-5 host implementation. The ATA (AT Attachment) interface, also known as IDE (Integrated Drive Electronics) interface, provides a simple interface to low cost non-vol
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
vga_lcd_latest.tar
- 此VGA/LCD控制器是revB.3版本的基于WISHBONE总线，适用于驱动CRT和LCD显示屏的嵌入式VGA驱动。-VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limit
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
wb_to_amba_latest.tar
- wishbone总线到AMBA总线的转换，做总线的朋友可以-wishbone bus to the AMBA bus conversion, so friends can see the bus
wb_conmax_latest.tar
- WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
led_driver
- LED display verilog code. to generate clocks and wishbone interface
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
wb_conbus
- wishbone的verilog代码的实现，标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
wishbone
- wishbone协议，IC设计必备 -wishbone agreement, IC design IC design must have the necessary
wb_flash_latest.tar
- its a flash controller which is compatable with wishbone
Digipot_wb_interface
- Generic Wishbone Slave interface for AD5204 driver. Instantiable in any platform.
i2c_latest[1].tar
- I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Mast