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wishbone_i2c_master
- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 200
adma
- Wishbone dma ip core
simple_spi
- 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchron
rs232_syscon_v
- This a state-machine driven rs232 serial port interface to a \"Wishbone\" // type of bus.-This a state-driven machine rs232 seria l port interface to a "Wishbone" / / type of bus.
wishbone_i2c_master_vhd
- WISHBONE revB2 compiant I2C master core
opencores_i2c_master
- i2c VHDL,能够实现I2C 用的是wishbone总线
Wishbone_from_opencores
- 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。
OptimizationofaDoubleWishboneSuspensionSystem
- This demo shows how to use MATLAB, Optimization Toolbox, and Genetic Algorithm and Direct Search Toolbox to optimize the design of a double wishbone suspension system.
SoC_WishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
opb_wb
- 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信， 从而使用基于Wishbone的许多开源IP Core
The_Analyse_And_Research_of_embeded_SoC_Bus
- 本文主要介绍和分析了在集成芯片设计中几种常用的片上系统总线－CoreConnect 总线、MBA 总线、Wishbone 总线和OCP 总线，通过比较这些总线的特性及适用范围，展望了它们的发展前景。
wisbone_2_ahb.tar
- ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Descr iption ---- ---- Implementation of Wishbone_
wb_rtc
- // -*- Mode: Verilog -*- // Filename : wb_master.v // Descr iption : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : U
wbspec_b3
- Introduce the wishbone bus .
SPI_Wishbone_Controller
- FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware descr iption language to achieve
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
eth_ocm_80_2
- ethernet wishbone interface
simple_spi.tar
- Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt gene
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
suanhenbi02
- 汽车悬架运动学仿真/双横臂悬架/可以自由下载-Kinematics Simulation of automotive suspension/double wishbone suspension/free download