搜索资源列表
RD1088_rev01.2
- FPGA或CPLD读取SD卡的IP核，基于wishbone接口，支持SDHC2.0，包含了使用说明，为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
Ethernet_MAC_10-100-Mbps_latest.tar
- The Ethernet IP Core is a MAC (Media Access Controller). It connects to the Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other. The core has been designed to offer as much flexibility as possible to all kinds of applications
ethernet_10ge_mac_latest.tar
- The 10GE MAC core is designed for easy integration with proprietary custom logic. It features a POS-L3 like interface for the datapath and a Wishbone compliant interface for management. The core was intentionally designed with a limited feature se
sd_verilog
- 关于sd卡的控制器verilog源代码，基于wishbone的总线协议
IDE_VHDL
- 此代码为wishbone公司的IDE协议主机端VHDL源代码，有三个版本，实现了UDMA。版权归wishbone公司，请勿用于商业用途。-This VHDL codes with threr versions implemented IDE host protocol，supporting with UDMA。
the-PCIE-interface-design
- 基于wishbone和端点IP的PCIE接口设计，介绍了PCIE硬核端点模块和wishbone总线规范，应用WHDL语言，编程实现了wishbone总线的主从端口-Based the PCIE interface design of the wishbone and the endpoint IP, PCIE hard core endpoint module and Wishbone bus specification, application WHDL language programmin
uart
- 基于wishbone的 uart 通信设计-The uart communication design based wishbone
rng
- wishbone规格下的rng代码的实现，自己编写顶层模块可以在modelsim下实现仿真-wishbone rng specifications under the implementation of the code, you can write your own top-level module under modelsim for simulation
WISHBONE_conmax
- 很详细的wishbone总线学习借鉴代码和文档-Very detailed wishbone bus to learn from the code and documentation
minsoc
- 片上处理器加上外设的设计,基于openrisc指令集，wishbone总线协议的一款基于FPGA的片上处理器-processor of on-chip
wb_dma_latest.tar
- 这是一个简单IP核的DMA桥，他有两个WISHBONE接口，该平台可实现在两个相同或不同接口之间DMA数据的搬运。-This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.
i2c_latest.tar
- i2C总线的控制器核，实现了I2C的主站功能。-I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol
jtag_memory_v0.12
- JTAG调试接口与testbench，附加memory模块并支持cpu和wishbone-JTAG TAP with Controller and testbench ,and an addition of block memory and the potential support of cpu and wishbone
i2s_latest
- Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL De
verilog_cordic_core
- A highly configurable 1st quadrant CORDIC core in verilog-Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other projec
I2C
- 一个基于wishbone总线的I2C控制器以及测试文件-wishbone I2C
i2c
- wishbone to avalon 介面 I2C-wishbone to avalon I2C interface
verilog-arbiter.tar
- Verilog arbitrator for Wishbone R3 compliant bus
wb_sdram_ctrl.tar
- Generic Wishbone R3 compliant SDRAM controller written in Verilog
wishbone_to_avalon
- wishbone-slave-and-master-to-avalon-bus,是关于wishbone总线和Avalon总线的转换，有实用价值，采用的是verilog编写