搜索资源列表
booth_mult
- 布斯乘法器的verilog实现及仿真文件,使用modelsim仿真-booth mult s verilog and test
qiyeshopping
- 设计一个企业电子销售管理系统，该系统的用户分别是： 会员和系统管理员。不同的用户拥有不同的权限，各自完成各自的管理功能，不同的用户看到不同的系统功能。用MySql创建后台数据库，然后利用JavaBeans编写程序实现对数据库的操作，用Struts控制业务逻辑层的跳转，为了调整系统的负载平衡用Ajax实现胖客户端来完成与数据库的异步交互，主要功能模块包括： 会员的主要功能模块包括： （1）会员管理（会员注册，会员登陆，会员资料修改） （2）商品展台（新品上架，特价商品）
6
- 该程序包含了完整的实体结构，实现的是一个K位xK位的布斯乘法器-The program includes a complete physical structure, to achieve a K xK-bit Booth multiplier
MirrorPicConsole
- 将图像转换为其镜像输出。可以处理mac的photo booth所照的镜像图片-transform a picture to its image in the mirror
Booth-co-so-2
- Radix Booh 2.nice to see u.i uploaded this file to download the file that i need actually
booth_mul
- 乘法器 基于改进booth编码 已验证 clk-multiplier modified booth
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘（Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现，通过Modelsim软件对相应的波形进行仿真验证，并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be a
mult_16
- 这是自己设计的16位乘法器设计，其中用了booth编码，，4-2压缩器等，-This is a 16 multiplier design of their own design, including the booth encoding 4-2 compression, etc.,
MIPS_final-version
- 以Verilog所撰寫的Booth’s Algorithm Multiplier，可加到NiosII CPU之上，完成一道NiosII CPU的新指令。-Written by Verilog Booth,' s Algorithm Multiplier can be added to the above NiosII CPU to complete a the Nios II CPU command.
pipeline
- 以Verilog撰寫而成的Booth’s Algorithm Multiplier，並以Pipeline方式實現。-Written in the Verilog Booth' s Algorithm Multiplier, and the Pipeline way.
Digital_multiplier_code
- digital_multiplier_code in VHDL (including CSA, Booth algorithm, wallace tree)
v16bbit_boothe
- verilog程序源码，实现两个16bit数乘法，使用booth算法，一种基于状态机实现，分层层次为datapath与controller两个子模块，testBench测试通过 -verilog program source code, and two 16bit multiplication using booth algorithm, based on the state machine implementation, the hierarchical level for the da
booth_mul
- 流水式BOOTH乘法器，包含整个工程文件，用Quartus9编写打开。为8bit乘以8bit乘法器-Flow BOOTH multiplier, contains the entire project file, open with Quartus9 written. Multiplied for 8bit 8bit multiplier
8-Multipliers
- 国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。-Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.
booth_multiplier
- 从google上下载到的booth乘法器-booth multiplier
multi16
- 有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。-Number system: 2 s complement Multiplicand length: 16 Multiplier length: 16 Partial product generation: PPG with Radix-4 modified Booth recoding Partial product accumulation: Wallace t
Unsigned-MultiplicationBooth
- 基于booth算法的移位操作，对带符号数进行乘法运算。-Shifting operation based on the booth algorithm, and the number of unsigned multiplication.
Mini-project-code1
- 4 bit booth multiplier is uploade
Assingment-1
- booth multiplier 8 bit
old_yasoda_code
- Jul 11, 2012 – Design of Efficient Multiplier Using Vhdl - download or read online. ... presents an efficient implementation of high speed multiplier using the array multiplier,shift & add algorithm,Booth ..... VHDL code for booth multiplier radix 4