搜索资源列表
DongHo
- design a clock using KIT DE1
Pong
- ping pong game fpga DE1
vga-example
- Basic VGA implementation on the Altera DE1
stopwatch9_02-_2---worked
- 一个基于DE1开发板制作的秒表，拥有启动，暂停，停止功能 内置寄存器，可以在计时是存储显示当前时间-DE1 development board based on the production of a stopwatch with start, pause, stop, features built-in registers that can be stored in the timing display the current time
audio1
- a good vhdl code for audio configuration altera de1 bored a good vhdl code for audio configuration altera de1 bored a good vhdl code for audio configuration altera de1 bored -a good vhdl code for audio configuration altera de1 bored a good vhdl code
First_test_Blinking_LEDs
- my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds -my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first
DE1_Default
- this the default setting for DE1 board that will reprogram the board to the default setting-this is the default setting for DE1 board that will reprogram the board to the default setting
DE1_SoC_i2sound
- FPGA控制麦克风播放语音程序,在DE1-soc开发板上面实现-FPGA control microphone to play the voice program, DE1-soc development board to achieve the above
DE1_Audio_AdcDac
- FPGA DE1 AUDIO ADC/DAC CODE
Controller
- Altera SoC ARM Baremetal Application for Terassic DE1-SoC Board
Altera_Audio
- 针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。-The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.
DE1_SoC_Audio
- 声音录制、播放的Verilog代码，用于Altera Cyclone V SOC. 写时适配的是DE1-SOC开发板。-Audio recording and playing code for Altera Cyclone V SOC FPGA. Code was designed for DE1-SOC development board, but could be reference for other boards.
DE1_SOC_ADC_test
- DE1中ADC Converter (AD7982)的值 可顯示在七段顯示器上-DE1 value in ADC Converter (AD7982) can be displayed on the seven-segment display
vga_verilog
- 在DE1-SOC上运行的verilog HDL代码，可以驱动VGA显示彩条。quartus II 14.0可以直接使用-Verilog HDL code running on DE1-SOC, can drive VGA display color bars. quartus II 14.0 can be used directly
VHDL_Examples_DE1_SoC
- DE1-COS学习例程,用VHDL语言为FPGA写入按键显示程序，有助于学习-DE1- COS learning routines, for FPGA with VHDL language display program written to buttons, helps to learn
SWITCH
- SWITCH(t,x,u,flag,e1,e2,e3,e4,de1,de2,de3,de4),多变量SWITCH函数-SWITCH FUNCTION
audio on fpga
- THis is the project that demonstrate the audio system on fpga basement. From this starting piont, other researcher can develop their own project easily
21
- 基于DE1的4位全加器（可视化），通过数码管显示，开关输入实现。-4 bit full adder based on DE1
Verilog_ex0
- 基于FPGA实验板的流水灯实验，实验板为DE1-Running water light experiment based on FPGA experimental board
Verilog_ex2
- 基于FPGA实验板的按键消抖实验，实验板选用DE1-Based on the FPGA experiment board keys away shaking