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T0424_auto_double
- 双核独立cpu分别控制流水灯（使用DE1开发板）(FPGA)-Dual-core independent CPUs control the water lights (using the DE1 development board)(FPGA)
ArkanoidFPGA
- 使用VDHL程式來設打乒乓球，並且操作，運用在DE1板子上-The VDHL program set to play table tennis, and operations, the use of the DE1 board
Altera-Lab-1
- Altera Lab 1 for DE1 - Manual and Solution
Altera-Lab-2
- Altera Lab 2 for DE1 - Manual and Solution
Altera-Lab-3
- Altera Lab 3 for DE1 - Manual and Solution
Altera-Lab-4
- Altera Lab 4 for DE1 - Manual and Solution
Altera-Lab-5
- Altera Lab 5 for DE1 - Manual and Solution
dice-game
- dice game in vhdl program, perform in hex and control by switch in kit FPGA alterna De1
TAlttera_SSDh
- 使用的Altera的DE1 的板子进行SD卡上音乐的读取。 -The use of Altera' s DE1 board to read music on the SD card.
tb_datargb_fifo
- tb_datargb_fifo.rar de1 project to test signal of the camera
nguyenvanduan_group4_TC304
- ASM chart for altera de1
audio
- 基于DE1开发板，实现录音和播放功能，并可将存入sram中的语言数据通过uart传回电脑。-Based on DE1 development board, recording and playback functions, and can be stored in sram language data back to the computer via uart.
SRAM_Controller
- sram control la FPGA KIT DE1
DE1lab1
- DE1 altera VHDL lab 1 exercise
DE1lab2
- DE1 lab2 altera Vhdl
as1
- Verilong HDL是最frequenctly使用的硬件描述语言，因为它的简单和方便的属性之一。这当然AIMES设计一个数字时钟，配备4段显示，秒表和时间设定使用这种语言，甚至一些额外的功能，fundamatal。 DE1板设计时钟的实施贡献-Verilong HDL is one of the most frequenctly used hardware descr iption language because of its simple and convenient propertie
DE1_synthesizer
- DE1 music synthesizer
FREQ-DIV-50MHz-to-64kHz
- Frequency divider implement on DE1 board, Clock in (OSC = 50MHz)to 64kHz
de1_camera_demo
- DE1 Demo Quartus Project (A Study of Spatial Color Interpolation Algorithms)
audio_latest.tar
- Audio Codec(ADPCM 1-Bit) The code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project. Core Descr iption: Sampling Frequency: 44100Hz Channels: Stereo Bit-rate: 1 Bit Per Sa