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DDS_report_1
- 16:1 MUX usind 2 4:1 MUX Strutures
mux
- Mulriplexer is implemented using VHDL.
mux4x1
- mux 4x1 with 2 control inputs, written in VHDL using 3 mathods: Logic gates, if, case. the fastest model is the one implemented with the case code.
vhdl
- Very high speed integrated Hardware Descr iption Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Descr iption Language (VHDL)-
mux
- Ciruit Design. A little application for designing a ciruit.
mxu_user_guide
- jz4740 多媒体指令指南，内含君正官方多媒体说明-jz4740 mux
mux4_case.tan
- mux 4 implement in cases
Inpout32
- 32 bit inout mux for embedded design
modulemux21
- 2 by 1 mux using verilog
AVIwenjianjiegoushilifenxi
- AVI文件结构实例分析——黄东军，贺宏遵 文章以二进制打开一个AVI文件详细解释了内部结构-AVI file structure example-黄东军, compliance贺宏article to open a binary file AVI explained in detail the internal structure of
ICT
- 96x96 Digital MUX/DEMUX via SPI
mux1bit
- A Mux to One Bit, written in VHDL.
Mux5-1
- Implementation of a 5to1 3-bit Mux
Mux4bit
- Implementation of a 4-bit mux
Mux2bit
- Implementation of a 2-bit MUX
4x1_mux
- verilog code for 481 mux
muxgen.pl
- mux generator written by perl
chap7
- 几十个经典程序，结构描述的4 位级连全加器，1 位全加器，用条件运算符描述的4 选1 MUX-Dozens of classic procedure, the structure described in the four-level with full-adder, a full-adder, using the conditional operator described in the four selected 1 MUX, etc.
mux
- VHDL realization of MultiPl
AVStream
- avstream vitual machine it can mux two different stream at same time and out to hardware stream