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66_FIR
- 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
CPLDOGRAM
- 摘要: 文中介绍了数字频率计的结构、工作原理及计数方式，给出了基于VHDL语言的频率计系统的行为源描述，讨论了在VHDL的高级综合系统QuartusII的支持下，自顶向下地进行传输模块的设计工程，并给出了系统的仿真波形以及其应用实践。-Abstract : This paper introduces a digital frequency of the structure and working principle and counting, is based on VHDL Frequency
quartusii
- 推荐!!!!!学ASIC相当不错的教程!!!!还是可以看看的-recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!
i2cvhdl
- i2c接口编程试验，quartusII开发-i2c Programming Interface testing, development quartusII
QuartusII_RAM
- 介绍了QUARTUSII中ram的应用，以及基于它的NIOS嵌入式小系统设计-were introduced QUARTUSII ram applications, and based on its small Nios Embedded System Design
QuartusII3.0
- QuartusII 3.0学习教程 ，chm文件，经典-study guides, chm, classic
ref-ualaw
- A率/u率 压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
硬件求解平方根
- 硬件求解平方根源代码加密 (硬件求解平方根的，将license添加到原有的MaxplusII或QuartusII的license中就可以直接使用，但源代码加密。altera提供 )-solving square root of the hardware encryption code (square root of the hardware solution will be added to the original license MaxplusII or Quartus II of the
CrackQII5.1
- altera quartusII v5.1 license
QuartusIIresistance
- 关于quartusII中如何设计上拉电阻的方法．-quartusII on how to design the widening resistance.
VerilogHDLPLI
- Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
pic16c57code
- 此代码可用modelsim进行仿真，修改rom之后可用quartusII进行综合，希望你们能对此程序不断完善。-modelsim this code can be used for simulation, After amending rom available quartusII comprehensive and hope that you can constantly improve this procedure.
QuartusII-detailed-crack-video
- QuartusII详细破解视频。对安装Q2有帮助。-QuartusII detailed crack video. Of installation Q2.
QuartusII-installation-instructions
- FPGA的开发软件QuartusII的安装与破解说明- QuartusII which is FPGA development software installation and crack instructions
10419729vhdl对数
- 进行对数运算的IP核，可以计算以2，10，e为底的对数，最高可输入24bit宽度的数据。 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。(The IP kernel that performs logarithmic operations can compute data at the base of 2, 10, and E, with the highest input 24bit width. Written in AHDL language, can
频率计
- quartusii 和vhdl语言利用四位频率计设计，(Four bit frequency meter design)
基于QuartusII的数字系统VerilogHDL设计实例详解
- 基于QuartusII的数字系统VerilogHDL设计实例详解(QuartusII based digital system VerilogHDL design examples)
para_norflash_altera_test
- 并行NORFLASH的verilog的quartusII工程，编译没问题，内含FIFO16*16(Parallel NORFLASH Verilog quartusII engineering, compile no problem, containing FIFO16*16)
led
- 使用quartusII实现verilog的流水灯编程(Use quartusII to implement verilog - flow lamp programming)
QuartusII原理图输入法设计VHDL组合逻辑电路设计VHDL时序逻辑电路设计
- QuartusII原理图输入法设计VHDL组合逻辑电路设计VHDL时序逻辑电路设计三个实验