搜索资源列表
Synopsys
- Synopsys 8051 IP core documentation.
vcs_simulation_mannual(Edition
- VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.,VCS-verilog compiled simulator is the Synopsys company s products. Its simulation at a fairly rapid pace, and support multiple call mode. This document is a good guide.
dw_apb_uart_db.rar
- 新思公司的uart数据手册，编写uart驱动必备的东东了，为公司内部资料。,Synopsys company uart data sheet, the preparation of the necessary Dongdong uart driver, and internal information for the company.
DW8051.rar
- Synopsys 公司的DW8051源代码，用verilog编写的，代码很完整，可以仿真，对采用8051核做嵌入式的人很有帮助,Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
The-Specification-of-SDC
- 综合约束文件SDC的写法说明 synopsys 出品-Using the Synopsys Design Constraints Format Application Note
vmm-1.0.1.tar
- VMM 文档加源码, synopsys公司很好的验证资料-VMM Document Canadian source, synopsys good company to verify the information
Synopsys_8051
- MCU_8051的Synopsys，到现在，我还没有用过-MCU_8051 of Synopsys, until now, I have not used
DC-RM_B-2008.09
- synopsys dc_shell 用户手册-reference manual of synopsys dc_shell
2008.09-scripts_only
- synopsys icc 使用参考脚本-reference scr ipt of synopsys icc
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
ICdesigntools
- IC设计工具很多，其中按市场所占份额排行为Cadence、Mentor Graphics和Synopsys。-IC design tools, many of them ranked by market share for Cadence, Mentor Graphics and Synopsys.
Saber2006
- synopsys公司！saber仿真软件，用于电路仿真。-synopsys Company! saber simulation software for circuit simulation.
Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design
- 使用synopsys design compiler和 prime time进行Asic开发的英文pdf-Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design.Compiler.Physical.Compiler.And.Primetime
VHDL
- vhdl 相关知识 指令及示例 和 Physical Level Design using Synopsys-vhdl command and example of relevant knowledge and Physical Level Design using Synopsys
ASIC_Design_Flow_Tutorial_with_synopsys
- Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
designcompiler
- its a descr iption collected to learn synopsys design compiler-its a descr iption collected to learn synopsys design compiler...
hspice_cmdref
- its a complete refrence for hspice synopsys tool-its a complete refrence for hspice synopsys tool..
synopsys_VCS_TOOL_flow
- this pdf file will gives the details of synopsys tool design space and verilog HDL ASIC design based tips.also this pdf is a power point presentation with functional verification tool of synopsys VCS tool.... VERY USEFULL FOR PROFESSORS