搜索资源列表
control0
- systemverilog编写的cpu读写mem程序-SystemVerilog prepared by the cpu readers mem procedures
fifo0
- systemverilog编写的fifo例子-SystemVerilog examples prepared by the fifo
SVDrink
- Systemverilog 编写的贩卖机代码-Systemverilog preparation for the sale code
SystemVerilog_FIFO_Channel
- 2004 SNUG of systemverilog
IEEE-Std-1800-2012-SystemVerilog
- IEEE Std 1800-2012 SystemVerilog - Unified Hardware Design, Specification, and Verification Language
SystemVerilog-Assertions-source-code
- SystemVerilog Assertion 应用指南一书的每章断言源代码，很好的SVA学习资料-SystemVerilog Assertion Application Guide for each chapter of a book asserts the source code, a very good learning materials SVA
Systemverilog
- 这个为systemverilog 的一个牛人的总结，是初学者必备的，很适合初学者运用的。-This is systemverilog a summary of cattle is essential for beginners, it is suitable for beginners to use.
SystemVerilog
- SystemVerilog设计(第二版) 用于编写TESTBENCH；-eetop.cn_SystemVerilog for Design(Second Edition)
SystemVerilog
- systemverilog语言介绍，例子，与应用-systemverilog language descr iption, examples, and Application
Based-SystemVerilog-ofAMBA-Bus
- 本论文是基于systemverilog的AMBA总线的实现，是学习systemverilog的一份好资料-This paper is based on systemverilog AMBA bus implementation, is to learn systemverilog a good information
Writing-TBusing-SystemVerilog
- 本书是关于如何用systemverilog写测试台程序的，对于搞验证和测试的人绝对有用-This book is about how to use the systemverilog write test bench program, for those who engage in verification and testing is absolutely useful
SystemVerilog 验证方法学
- systemverilog 验证方法学，夏宇闻版(systemverilog verification methodology)
SystemVerilog
- 有三篇systemVerilog的经典书，对学习很有帮助(There are three classic books of SystemVerilog, helpful for learning)
THE_UVM_PRIMER_CODE_EXAMPLES.tar
- The exmaples for the ebook The UVM Primer An Introduction to the Universal Verification Methodology by Ray Salemi The UVM Primer is the book to read when you've decided to learn the UVM. The book assumes that you have a basic knowledge of SystemVeri
SystemVerilog断言及其应用
- 该书用来阐述如何使用断言，以及断言的语法和示例(The book is devoted to the use of assertions, as well as to the syntax and examples of assertions)
SystemVerilog 3.1a中文+英文版
- Sytem Verilog 语言的设计事项(SystemVerilog user Guide)
SystemVerilog for Design(Second Edition)
- 本文档用于使用systemverilog系统硬件描述语言做ASIC设计，深入浅出，易懂(The doc is using systemverilog system harward descr iption language to do ASIC design.The doc is easy to read,for new bird in this fact.)
SystemVerilog验证 测试平台编写指南
- systemverilog编程资料，用于验证(doc of systemverilog, for chip verification)
systemverilog+assertions应用指南
- system verilog assertion介绍(system verilog assertion introduction)
高级验证方法学(AVM)中文版
- AVM（高级验证方法学）验证手册，是用SystemVerilog和SystemC两种语言实现的。(AVM (Advanced Verification Methodology) verification manual is implemented in system Verilog and system C.)