搜索资源列表
uvm
- the Universal Verification Methodology (UVM) for creating SystemVerilog testbenches.
vmm
- verification methodology manual 英文原版和 论文《基于VMM的芯片验证平台设计》-verification methodology manual for systemverilog
sdram_sv
- sdram在quartus下的VerilogHDL描述，准确的是SystemVerilog，已调试成功，不过还没利用突发传输功能，内含modulesim的仿真文件。-sdram VerilogHDL under the quartus descr iption is accurate SystemVerilog, has been commissioning successful, but not using burst transmission, the simulation file con
syn_fifo
- 同步FIFO的源代码（单时钟），使用SystemVerilog语言实现-Synchronous (single clock) FIFO，using SystemVerilog
ram_sp_sr_sw
- 同步读/写 RAM，使用systemverilog实现-Synchronous read write RAM, using systemverilog
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
SystemVerilog
- 初学者实现规范Verilog代码的必备手册-HDL stye
Verification_of_UART
- 使用Systemverilog语言对UART进行验证，其中UART代码为verilog语言-Use Systemverilog language UART to verify which code for verilog language UART
SystemVerilog-for-Verification
- 经典的system verilog 教程。英文原版。-system verilog english version ， very useful
SystemVerilog
- System Verilog中英文资料大全（pdf文档）-System Verilog Sourcebooks of Chinese and English (pdf document)
SystemVerilog31a_cn
- 这是一本systemverilog的手册欢饮下载-This is a systemverilog manual are welcome to download
synopsys_verification
- 这是synposys关于systemverilog的使用向导-This is synposys SystemVerilog using the wizard
VMMing_Testbench_by_Example
- 基于VMM的验证实例，描述了对一个fifo的验证平台-a systemverilog testbench for vmm
VHDL-Verilog-Systemverilog
- 解决初学者疑惑：VHDL、Verilog，System+verilog比较,适合初学者对三种语言的理解-Solve beginners doubt: VHDL, Verilog, the System+ Verilog, suitable for beginners understanding of the three languages
SVA-script
- 一个自己总结的systemverilog assertion读书笔记，基本上systemverilog assertion的语法比较全。简单易懂。适合SVA入门。-systemverilog assertion scr ipt
SystemVerilog
- 比较经典实用的system verilog教程，值得参考-More classic and practical system Verilog tutorial, it is worth
ces_svtb_2011.12
- synopse sv培训lab，是学习systemverilog非常好的资料，放心下载。-synopsis sv training lab
System-Verilog-and-HDL-skills
- 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UM
uvm-1.1d.tar
- UVM World 官方发布的UVM（通用验证方法学）的源代码，基于SystemVerilog，用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
spi_final_presentation
- Implement SPI Master and SPI Slave cores (VHDL) Implement Master and Slave hosts (VHDL) Verify the entire design (SystemVerilog)