搜索资源列表
uvm
- UVM验证平台的介绍，在验证方面效率由于systemverilog。-UVM verification platform introduced in verification efficiency due systemverilog.
switch_9
- 使用systemverilog语言写的4端口交换机，你可以学习使用systemverilog-use systemverilog write 4 port switch,you can learing systemverilog language
rank_exam
- 基于systemverilog的高考学生个人信息数据库，并带有排序功能-Based systemverilog entrance pupil personal information database, and with the sort function
memory
- Systemverilog实例，可以作为实战项目练习！-Systemverilog instance, you can practice as a real project!
VerilogaSystemVerilog
- 关于Verilog与SystemVerilog之间的区别，有相关代码，希望对大家理解其区别有所帮助~-Verilog and SystemVerilog on the differences between the relevant code, we want to be helpful to understand the difference ~
sutherland_FIFO_final
- Modeling FIFO Communication Channels Using SystemVerilog Interfaces
california_university_8051_cPPmodel
- 加州大学研究生做的8051 C++模型，用于8051cpu的仿真验证。可作为的systemverilog中调用的golden model使用-University of California graduate student doing 8051 C++ model for the simulation 8051cpu. Golden model can be invoked as a systemverilog use
Blackjack
- Blackjack program VHDL program SystemVerilog
John-Havlicek-Presentation
- FSL SystemVerilog Requirements Requirements on basic constructs and types Requirements on assertions Requirements on external capabilities Requirements on hierarchy Requirements for AMS High
sv-reference-doc
- systemverilog入门 用于IC验证-for test
SystemC
- System C FPGA仿真软件,与SystemVerilog配合-System C for FPGA
systemverilog
- 是关于System Verilog的课件，简要介绍了了System Verilog的用法，主要介绍进行可仿真和可综合的硬件设计，作为Verilog的扩展，在抽象设计、测试平台和基于C语言的应用程序设计接口有重大改进。-About System Verilog courseware, brief introduction of System Verilog usage introduces conduct can be integrated simulation and hardware desi
viterbi-systemverilog
- viterbi decoder (2,1,7)(133,171)-viterbi decoder (2,1,7)
AES
- AES代码 加解密代码 systemverilog编程-AES code
SV_Guidelines
- SystemVerilog Coding Guidlines
ahb_master_agent
- Ahb master agent in systemverilog
ahb_slave_driver
- Slave driver in systemverilog for AHB
eth_mac_frame
- Class file to handle creation of Ethernet frame content SystemVerilog Language
UVM_Golden_Reference_Guide
- The UVM Golden Reference Guide is a compact reference guide to the Universal Verification Methodology for SystemVerilog. it offers answers to the questions most often asked during the practical application of UVM in a convenient and concise ref
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output