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FPGA_DDR_SDRAMverilog
- 基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex-4，实现对DDRSDRAM的简单控制（对一系列地址的写入和读取）。-Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to wr
Xilinx_TMR_XVRWARE_Library
- XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture
virtex5
- virtex-5_设计注意事项(中文)。主要介绍DSP-48E的设计技巧。-virtex-5_ design considerations (English). Focuses on the design of DSP-48E skills.
soc-OverviewProcessors.pdf
- 几款处理器相互比较，包括EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)-OVERVIEW-EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
xapp946
- Switching Power Supplies for Virtex-4 RocketIO MGTs
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
Rocket
- 很好的高速口的设计资料，很好的高速口的设计资料 很好的高速口的设计资料-In design of large-scale access convergence router(hereafter referred to ACR) forwarding engine, the Xilinx Virtex-4 FPGA!s RocketI/O r multi-gigabit transceiver is used to satisfy the need of high speed and st
ddr_sdr_V1_1
- DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted
xapp737
- xapp737 from xilinx website : SPI-4.2 to Quad SPI-3 Bridge in Virtex-4 FPGAs
VHDL_RAM
- Virtex II pro RAM memory
VHDL_UART
- Virtex II pro UART RS232
VHDL_VGA
- Virtex II pro VGA control
pBlazIDE36
- There are literally dozens of 8-bit microcontroller architectures and instruction sets.Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as
FPGAIMPLEMENTATIONOFATUNABLEBANDPASSFILTER
- Any Band-Pass filter may be converted into a tunable filter with a single tuning parameter through the use of a new Tunable Heterodyne Band-Pass Filter concept in which the frequency of the heterodyne signal is adjusted thereby translating the
xapp1014_c5_GTP_SDI_RX
- Audio&Video Connectivity Solutions for Virtex-5 FPGAs
GeneratingFPGA-AcceleratedDFTLibraries
- 关于DFT的文章，应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT
ds202
- virtex-5系列的AC和DC特性，包括DCM的性能和管脚的电气标准-virtex-5 Series of AC and DC characteristics, including the performance of DCM and pin electrical standards
OFDM_Security
- This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA. The RAR file inlcudes 2 files: 1. Simul
virtex5
- Virtex® -5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is l