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通用存储器包括各种类型存储器的VHDL描述
- 通用存储器包括各种类型存储器的VHDL描述, 如FIFO,双口RAM等VHDL代码库
read_wirte_ram
- FPGA实现双口RAM功能,从而用FPGA实现双控制器间的数据交换-FPGA realization of dual-port RAM functions, the exchange of data between the dual-controller with FPGA
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程,可实现2k8的双口ram,实现数据存储,缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
dual_ram
- FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
ramFIFO
- 双口RAM实现FIFO程序解释,说明.-FIFO dual-port RAM procedures to achieve explanation. Good
ram
- 一个用VHDL语言编写的双端口存储器程序,可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using
caiji1
- 利用两个双口ram做的乒乓操作,采集高速大容量数据,fpga写,arm读-Two dual-port ram to do the ping-pong operation, collecting high-speed large-capacity data, fpga write, arm reading
13
- para13: fifo.vhd FIFO(双口RAM) fifo1.vhd FIFO(嵌入式EAB) fifo2.vhd FIFO(LPM)-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
udp_pack_nios
- Nios II打包程序,通过DMA把接到AVALON从接口的双口RAM数据传到片外的SDRAM,再用UDP打包进行以太网传输-Nios II pack
jj
- 本题设计一个数字存储示波器,以Xilinx公司20万门FPGA芯片为核心,辅以必要的外围电路(包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块),利用VHDL语言编程,实现了任意波形的单次触发、连续触发和存储回放功能,并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时,将外部输入信号经信号调理模块调节到A/D电路输入范围,经A/D转换后送入FPGA内部的双口RAM进行高速缓存,并将结果通过D/A转换送给通用示波器进行显示,完成了对中、低频信号的实时采样和高频信号的等效采
Example-b4-1
- Altera基本宏功能的产生和实现方法.定制一个双端口RAM,DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on t
RAM2x64C_1
- 双口RAM用于数据存储和读取,在FFT处理器重,快速的读取和存储数据,可以提高处理器速度-Dual-port RAM for data storage and reading, in the FFT processor heavy, fast read and store data, can improve the processor speed
dp_ram
- 双口RAM的设计,采用Verilog HDL语言编写。-Dual-port RAM design, using Verilog HDL language.
The-pulse-signal-generator
- 脉冲信号发生器:采用DDS技术实现脉冲信号的周期、脉冲宽度、幅值的数控调节。通过单片机与FPGA的并行通信技术将频率控制字及矩形脉冲数据传送给FPGA的双口RAM。模拟输出通道则将信号通过100MHz、8位D/A转换器将波形数据转换成模拟脉冲信号,最后通过高速运放构成的放大器放大,实现幅度连续可调。-The pulse signal generator: using the DDS technology to achieve the pulse signal cycles, pulse widt
Abus_fifo_ram_V1
- 该模块是基于verilog语言编写的双口ram模块,可将该该模块作为缓存模块使用-surpost ram write/read
memory_cores
- 通用ram源码包,包括双口ram,单口ram,fifo等-general ram source package,include dual port ram,single port ram,fifo,etc.