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piso10
- 很有用的10bit并串转换程序,在quartus上已验证过,需要的可以拿去-10bit and useful string conversion process has been verified in quartus need to take to use with
ofdm-fangzhen
- OFDM 的仿真程序,包括调制,并串转换,ifft,并串,加前缀,fft,解调,-OFDM simulation program, including modulation, parallel to serial conversion, ifft, and string, prefix, fft, demodulation,
I2S
- 此设计主要是完成音频I2S格式数据流的串并转换和并串转换,用VHDL描述-This design is to complete the audio I2S format data stream serial to parallel conversion and parallel to serial conversion in VHDL
para_serial
- 利用Verilog语言实现串并转换和并串转换,方便CPU和单片机之间通信 -Verilog to implement a serial-to-parallel conversion and parallel-to-serial conversion, to facilitate communication between the CPU and the microcontroller
multiplex
- 四路信息时分复用和解复用,包含串并转换,并串转换,提取帧同步,分频,移位寄存器。-Quad information time-division multiplexing and demultiplexing, contains the string conversion, parallel-serial conversion, extracting the frame synchronization, frequency division, the shift register.
ps_transfer
- verilog HDL语言编写的8位并串转换,使用状态机实现可综合-Using verilog HDL language realize parallel-to-serial conversion, using the state machine to achieve ,can comprehense
parallel8_serial
- V5 FPGA中8:1并串转换输出,可供初学者参考设计,涉及 OSERDES 原语的使用-the use of "OSERDES"
para2serial
- 并串转换模块,用于serdes编码器后面的部分,转换后用于LVDS发送。-And string conversion module, part of the back of the encoder for serdes, after conversion to LVDS transmitter.
74HC165
- 8051系列单片机控制74HC165并串转换-c51程序-8051 Series MCU control 74HC165 and string conversion-c51 program
serial_to_para
- verilog状态机实现并串转换serial_to_para,本人已调试并仿真成功,绝对可用-verilog state machine and string conversion,i think it is very important to someone who is ready to learn verilog
turbo_encode
- 移动通信技术中信道编码的并串转换的Verilog hdl 实现-Channel coding of mobile communication technology and the string conversion of Verilog hdl realization
a-design-of-8b_10bSerDes
- 。论文首先给出了8b/10bSerDes的系 统结构,将其分为发送端和接收端两个部分,然后按照功能的不同,对电路进 行了模块划分,并且设计了其中的4个主要模块.8b/10b编码模块、8b/10b解码 模块、10:1并串转换模块和1:10串并转换模块。-A Design of 8b/1 0bSerDes
decoder-SerDes
- 介绍了8b/10b SerDes 中数字模块的设计和验证,这些数字模块 包括:8b/10b 编解码器、Comma 检测器和串并/并串转换电路。-This article introduces theories and applications of four types of SerDes architecture, and establishes the design of 8b/10b SerDes interface circuit through a top-down des
OFDM
- OFDM系统仿真,包含串并转换,QAMmap,IFFT转换,并串转换之类。-OFDM System Simluation
Example-s1-1
- 面积和速度的互换是FPGA/CPLD设计的一个重要思想。从理论上讲,一个设计如果时序余量较大,所能运行的频率远远高于设计要求,那么就能通过功能模块复用减少整个设计消耗的芯片面积,这就是用速度的优势换面积的节约;反之,如果一个设计的时序要求很高,普通方法达不到设计频率,那么一般可以通过将数据流串并转换,并行复制多个操作模块,对整个设计采取“乒乓操作”和“串并转换”的思想进行处理,在芯片输出模块处再对数据进行“并串转换”。从宏观上看,整个芯片满足了处理速度的要求,这相当于用面积复制换取速度的提高。面
bd_psk_decoder20150303
- 对DQPSK调制解调技术的FPGA实现进行了比较全面的研究,利用nQpSK调制技术实现了码速20oKbps的调制器。调制载频3.2MHz、带宽18oKHz、带外抑制大于45dB,调制器设计达到预定要求。解调器硬件完成,软件未全部实现,但完成了CIC滤波器、载波跟踪环、位定时同步、并串转换等几个关键模块的设计。对解调器做了实验测试,验证了相关模块设计的正确性,解调器中重要的载波同步功能己能实现-DQPSK modulation and demodulation techniques for FPG
chuanbing-and-bingchuan
- 基于FPGA的通信,实现串并并串转换,简单容易理解,代码完整,希望对你们有帮助-FPGA-based communication, and achieve string and string conversion, simple and easy to understand, code integrity, and I hope you have help
parell_to_serial
- 并串转换代码,8位并行输入,1位串行输出-Serial conversion code, 8-bit parallel input, a serial output
FPGA__source-code__Verilog
- FPGA部分基础功能源代码,适合初学者进行学习仿真,代码可读性强,通俗易懂,逻辑清晰。包括触发器,全加器,分频,并串转换,计数器,序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
piso8_ok_bingchuanzhuanhuan
- 本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)