搜索资源列表
PLL
- 基于TMS320F28335的全数字锁相环的设计-The design of the digital PLL based on TMS320F28335
Matlab-about-pll
- 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全 数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable t
verilog
- 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
SHUZIPLL
- 关于数字锁相环的一篇文章,详细说明了数字锁相环的原理，还有仿真-Article on digital phase-locked loop, the detailed descr iption of the principle of a digital phase-locked loop, as well as simulation
suoxiang
- 电力并网数字锁相环(PLL)程序，简单可靠 -Electricity grid digital phase-locked loop (PLL) program, a simple and reliable
ADLL-verilog-code
- 数字锁相环的设计代码，完整的，希望能帮到大家-PLL phase-locked loop
DCO_ST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DPLL_TEST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DLF
- 可增可减的计数器，可以用于全数字锁相环中的环路低通滤波器-Either upwards or downwards counter low-pass filter can be used for all-digital phase-locked loop in the loop
paper3
- MPSK解调的关键在于载波同步和码元同步．这里采用 数字锁相环实现载波同步和码元同步.pdf-MPSK demodulation key symbol synchronization and carrier synchronization. Here digital phase-locked loop carrier synchronization and symbol synchronization. Pdf
PLL
- 三相数字锁相环pscad仿真 dq算法 PI控制-Three-phase digital phase-locked loop simulation in pscad
PLL_success
- 数字锁相环，曼彻斯特的产生与解码,verilog hdl-Digital PLL, Manchester generation and decoding, verilog hdl
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
ADPLL-patent
- 全数字锁相环的几个专利，全部为英文，很好的参考资料-DPLL patent
test
- VHDL语言实现数字锁相环，方法为超前滞后法-VHDL language digital phase-locked loop, and methods for lead-lag method
pll1
- 数字锁相环matlab编程代码，适用于初学者进行参考，欢迎大家下载！-Digital phase-locked loop matlab programming code, suitable for beginners reference, welcome to download
PLL
- 一种基于数字锁相环的matlab的程序仿真代码-Based on digital phase-locked loop matlab simulation
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
digital-PLL
- 收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。-Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.
pll_zsy.v
- 全数字锁相环程序 此程序基于VHDL编写 可以完成相关功能-All digital phase-locked loop based on VHDL write program this program can complete the relevant function