资源列表
排序选择：
SD_initcode
- SD初始化部分 有利于对SD有一个初步的认识-SD initialization part of SD to a preliminary understanding
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
dirital_clock_7
- verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
dff_UDP
- verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a descr iption of the fringe is triggered D flip-flop, test test pass
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
I2C_verilog
- I2C总线verilog实现源码，可以完整实现I2C bus的基本功能-I2C Bus verilog achieving source, I2C bus integrity of the basic functions
BCBDES
- 是用C++ Builder 写的DES加密算法.-C Builder is written by the DES encryption algorithm.
DelphiTimer
- 一个使用Delphi编写的精确计时程序.-a precise timing of the preparation procedures.
vc1020345346241_newa
- 一个简单的画图程序 试试看 能画直线 画圆 画矩形 可以 调整线宽 可以复制粘贴-a simple drawing program can try painting Circle Line painting rectangular width can be adjusted copy paste
NewsDemo
- 我在东软培训期间的小联系-I Neusoft training in the small links!
DelphiTuoPan
- 使用Delphi编写的托盘例子程序，很基础的啦。-use Delphi procedure trays example, the very basis of Matata.
HTMLAna
- HTML analyze 分析HTML的内容-HTML analyze the content analysis of the HTML