资源列表
排序选择:
capword
- 通过Hook实现屏幕取词,虽然功能以前有人已经实现,但是,这段程序经过稳定性测试,可以进入商用,希望大家下载。-Introduction Capture words on screen with \"Hook\", which has already been realized, however this program has bben carefully tested and can be adopted in commercial use. Welcome to download!
dds_quicklogic
- 直接频率合成,Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP
显示0到F
- 利用串行驱动数码显示每位从0显示到F,到灭循环显示,要求1秒更新一次。-drive using serial digital display shows each from 0 to F, to eliminate cycle, a request updated seconds.
局部换肤
- 可以实现局部换肤。 与传统的换肤不同的是,他不是将整体界面换肤,而是将其中的一个Frame,button,text换肤。-can achieve partial Eurocargo. With the traditional Eurocargo different is that he is not the overall interface common. Instead of the one frame, the button, text Eurocargo.
洗衣机
- 通过不同的二极管亮,表示洗衣机的不同状态。如正转、反转、洗条、干衣。按下P3_3时,会停止。 -through different diode light, washing machines, said the different states. Who is changed, and turned around, washing, drying. Press P3_3, would cease.
ddr_verilog_xilinx
- DDR(双速率)SDRAM控制器参考设计,xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
红绿灯
- 模拟交通灯,并带有数字显示的程序。初始时全为红灯,显示“HELLO”字样。然后交通灯以“红绿、红黄、绿红、黄红”四种状态做循环,而且黄灯会闪烁,每种状态都带有到数记时。当按下P3_2时,变成“红红”状态,并显示“STOP”字样! -simulated traffic lights and figures with the procedure. When all of the initial red, shows that the "hello" words. Then t
DS12887时钟芯片编程
- 利用程序中的函数,来读取时钟芯片的秒、分、时、日、月、年、世纪,亦能对其设置时间日期。-procedures for the use of function, to read clock chip seconds, hours, days, months, years, centuries, but also the date of its set-up time.
CRC校验参考设计_xilinx_vhdl
- 可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
电子节拍器
- 捕捉拍频 * 捕捉拍频功能仅在拍子停止时可用。 * 以一定节奏连纽按动Tap按钮两下或更多,Tempo会自动对应于按动的拍频。 * 连续2秒没有按动Tap,或启动拍子,则上次按动的记录将被清除,并在下次按动时重新记算拍频。 * 拍频将以连续按下的拍子间隔,以一定算法进行统计,得出近似值。 调节音量 * 拖动Volume框中的滑条即可调节音量,向左拖动使音量减小,向右拖动反之。 * 最小音量为静音,最大音量为拍音的原音量。 运行模式 * 选择Rum
LogProc
- 是一个Dos控制台程序,可以将一个非常大的文件,如2G的文件分割成几百个小的文件,对于日志察看非常有用。-Dos console is a process, which would be a very large documents, such as 2G in the paper is divided into hundreds of small files and log look very useful.
CRC校验参考设计_xilinx_verilog
- IEEE 802.3 Cyclic Redundancy Check参考设计,xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx