资源列表
程序案例LabVIEW上实现虚拟示波器
- 程序案例LabVIEW上实现虚拟示波器位全加器. .............................\3位二进制译码器.vi .............................\4选1数据选择器.vi .............................\RS触发器.vi .............................\RS触发器仿真过程.vi .............................\时钟.vi .................
（2,1,3）卷积编码和viterbi译码
- 自己写的（2,1,3）卷积编码器和viterbi译码，测试已通过
DDR3_SDRAM
- ddr3 sdram 功能测试。读写测试还有自刷新测试，测试通过。-ddr3 sdram test,write and read ,aoturefresh
SIN_COS
- fpga产生正弦波形，sin_cos，modelsim仿真通过-fpga generate sin waveform,test passed
LED
- 简单的流水灯设计，四个灯轮流闪，测试通过-led test， shift
USB_GPIF-II
- fpga模拟两路视频，简单拼接后，经过GPIF II接口传出给cy2014，测试usb的吞吐量-fpga generate two lane video, and transmit them through GPIF II interface. test cy2014
9363
- AD9363控制接口,在TDD模式下，cmos接口传输数据，数据率61.44MHz，时钟122.88MHz-ad9363 interface.tdd mode.
qiangda
- 抢答器，3人进行抢答，即对应三个开关，谁先按下，LED输出显示-Responder, 3 answer, that corresponds to three switches, who first press, LED output display
cla_16bit
- verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
pwm_generate_module
- verilog编写的，用按键控制PWM波占空比。可以定义死区，用来控制舵机或者led灯的亮暗。-Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
async_fifo
- 用verilog编写的简单异步fifo。可以给初学者用来学习fifo的初步工作原理。（不能直接使用。）-Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)
Butterfly_lovers_beef
- verilog编写的蜂鸣器音乐《梁山伯与祝英台》。系统时钟为50MHz。-Verilog prepared buzzer music Butterfly Lovers . The system clock is 50MHz.