资源列表
eeprom_test
- EEPROM 读写例程， IIC 的通信程序 iic_com.v，顶层文件 eeprom_test.v(EEPROM read and write routine, IIC communication program iic_com.v, top level file eeprom_test.v)
uart_tx
- 串口 Uart 通信例程，接收程序设计，Uart 接收程序包含 3 个程序, 分别是时钟产生程序 clkdiv.v, 串口发送程序 uarttx.v 和串口接收测试程序。(Serial port Uart communication routine, receiving program design, Uart receiving program contains three programs, respectively, clock generation program clkdiv.v, s
uart_test
- 串口 Uart 通信例程，发送程序设计，Uart 发送程序包含 3 个程序, 分别是时钟产生程序 clkdiv.v, 串口发送程序 uarttx.v 和串口发送测试程序。(Serial port Uart communication routine, send program design, Uart send program contains three programs, respectively is the clock generation program clkdiv.v, seria
ADC
- this is a stm32 adc demo
8-bits-RISC-CPU-Verilog-master
- RISC精简指令集计算机相较于CISC复杂指令集计算机能够在一个时钟周期执行更多的指令，这些指令比CISC的指令集具有更短，功能更简单，指令格式更统一等特点，因此适合流水线处理，加快处理速度。(RISC Reduced Instruction Set Computer can execute more instructions in one clock cycle than CISC Complex Instruction Set Computer. These instructions are
FPGA对W25Q16读写
- FPGA对W25Q16读写FPGA对W25Q16读写FPGA对W25Q16读写FPGA对W25Q16读写
rtc
- rtc的资料，里面的东西不少，目前还没有完全看明白。
rtl
- IIC SLAVE的简单例子。可以直接用于FPGA验证(an iic slave sample. can use by FPGA)
iic
- 通过iic总线实现数据的读和写，以及基于的modelsim测试。(Through the iic bus to achieve data reading and writing,and based on the modelsim test.)
FILTER
- 卡尔曼滤波库，可调参数达到最优，已经验证并用于工程应用(Kalman filter library, adjustable parameters to reach the optimal, has been verified and used in engineering applications)
第三次实验
- 3-8编码器，基于verilog实现，初级程序(3-8encoder,Based on Verilog implementation,the primary program)
uart1
- 电脑通过串口发送不同的命令，控制不同的花样流水灯，串口包括校验和波特率的配置(The computer sends different commands through the serial port, which includes the configuration of check and baud rate)