资源列表
FIR-Filter-using-Precomputation-Block-master
- vivado2017.4两个定点数相乘的程序，testbench和上板验证(Based on vivado 2017.4, this program multiplies the number of two fixed points and compiles the simulation file testbench)
RGB
- 基于nexys4 DDR的RGB呼吸灯点亮程序，已上板验证(RGB breathing lamp lighting program based on nexys4 DDR has been verified on the board)
test2017_4
- 基于vivado2017.4 使用开关改动led灯的亮灭并配合testbench仿真(Based on vivado 2017.4 using switch to change the light of LED lamp and cooperate with testbench simulation)
isenexys4xadc
- Nexys4DDR板子的约束文件，编程接口可自定义(Constraint file of nexys4ddr board, programming interface can be customized)
CPU_SELF_monocycle
- 设计一个单周期CPU，该CP能实现基本的r型，j型的指令功能操作。(A single cycle CPU is designed, which can realize the basic R-type and J-type instruction function operation.)
0_17_EEPROM
- 在FPGA上实现E2PROM的读写配置操作，使用Modelsim带有仿真模型(The reading and writing configuration operation of E2PROM is implemented on FPGA, with simulation model using Modelsim)
0_19_Sdram_Control
- 用Verilog语言实现SDRAM的初始化配置和读、写、刷新的操作，带Modelsim仿真模块(Using Verilog language to realize the initial configuration of SDRAM and the operation of reading, writing and refreshing, with Modelsim simulation module)
0_18_SCCB
- 用Verilog语言实现摄像头OV7670的接口配置时序SCCB协议(Using Verilog language to realize SCCB protocol of interface configuration of camera ov7670)
0_10_uart_rx
- 在FPGA板卡上面，实现串口的发送功能，带仿真需要自行修改一下工程配置(On the FPGA board, realize the sending function of the serial port. With the simulation, you need to modify the engineering configuration by yourself)
0_09_uart_tx
- 在FPGA板卡上面，通过单个按键实现串口的发送功能，带仿真需要自行修改一下工程配置(On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation)
mul_bus8
- An multiplexer with 8 inputs
sum_compt8
- Adder of 8 inputs with an multiplexer