资源列表
spi
- spi的串口简单数据通信实验，实现数据发送(SPI serial port simple data communication experiment, to achieve data transmission)
异步FIFO
- 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
hdmi
- 滚动彩条显示。通过HDMI接口输出单色图案、渐变色、单幅马赛克、动态马赛克等图案。使用Verilog，基于Xilinx Spartan-6 LX45器件，AX6045开发板(Scroll bar display. Through HDMI interface output monochrome pattern, gradient color, single mosaic, dynamic mosaic and other patterns. Using Verilog, based on Xil
AXI slave
- AXI slave 完整 verilog代码。测试验证通过。
22
- 《数字滤波器的MATLAB与FPGA实现：Altera Verilog版》——杜勇六到九章pdf(Realization of digital filter with MATLAB and FPGA: Altera Verilog version)
21
- 《数字滤波器的MATLAB与FPGA实现：Altera Verilog版》——杜勇前五章(Realization of digital filter with MATLAB and FPGA: Altera Verilog version)
1
- 数字通信同步技术的MATLAB与FPGA实现 Altera Verilog版.pdf(Synchronization technology of digital communication MATLAB FPGA Altera Verilog.pdf)
10101011110序列检测
- 1.画出检测序列1010101110的状态转换图,并且使用veriogHDL写出相应程序
译码器5-18
- 用veriloghdl设计的5-18译码器，可用于流水灯的设计
FLASH_model
- 模拟flash读写等时序，学习如何操作该芯片，芯片是n25q系列，欢迎大家下载学习
AHB5-master
- amba ahb2 协议vip，包括master和slave(AMBA AHB 2.0 VIP in SystemVerilog UVM)
AHB2-master
- AMBA AHB 2.0 VIP in SystemVerilog UVM