资源列表
eda2
- 7段显示译码器的输入为：IN0…IN3共5根， 7段译码器的逻辑表同学自行设计，要求实现功能为：输入“ 0…15 ”（二进制），输出“ 0…9…F ”（显示数码），输出结果应在数码管（共阴）上显示出来。-failed to translate
FPGA-based-display
- 基于FPGA的四位数字循环动态数码显示，内含100M分频器-FPGA-based digital loop two-digit display
Debouncer_Ver2
- super fast debounce button on vhdl, xilinx xc
ca60
- 60分频器，将主频分频，产生系统所需信号。-60 divider, the frequency divider to generate the necessary signal system.
shift_reg
- Shift reg in vhdl, a first example to start
N_Bit_CLA_4.0.vhd
- N-Bit Carry Look Ahead adder
2
- 使用变量的状态机 library ieee use ieee.std_logic_1164.all ENTITY fsm2 IS PORT(clock,x : IN BIT z : OUT BIT) END fsm2 ------------------------------------------------- ARCHITECTURE using_wait OF fsm2 IS TYPE state_type IS (s0,s1,
pri_encoder_using_if.v
- this is a verilog source code for priority encoder using if statement.
virtex5-C
- 使用FPGA VIRTEX5 板子做演化硬件时SDK平台中C语言描述。-FPGA VIRTEX5 C
bin2bcd
- Binary to BCD converter
t1
- 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M gr
decode3to8
- Decoder3to8 in vhdl. Behavioral solution.