资源列表
shuzizhong
- 大学VHDL实验数字钟源码，有的专业数字电路实验设计也有要求做的。-University of VHDL experimental digital clock source, and some professional digital circuit design has also requested to do so.
seriall2parallel
- its code for converting serial to parallel processing data
gold
- 基于vhdl语言的15位gold序列的设计的开端一部分程序-Vhdl language based on sequences of the 15 gold as part of the beginning of the design process
jjj
- 库文件实现的单片机的转换 我也不是很清楚-it is a file sorry i do not konw what is is?
RAM_VHDL
- 用VHDL描述了一个32KBit的独立的读写时钟、使能、地址的双口RAM，-VHDL descr iption of a 32KBit with independent read and write clock, enable, address the dual-port RAM,
fenping_VHDL
- 这是一个任意分频器 稍微改动里面的数据 就可以进行分频（VHDL编写）-This is a slightly altered any data inside divider can be divided by (VHDL written)
BTO
- 这是一个十六进制显示译码器，可在EDA板子上实现，希望对大家有帮助-This is a hexadecimal display decoder may be implemented on EDA board, we hope to help
practica1
- tester.vhd library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all LIBRARY lpm USE lpm.lpm_components.ALL entity practica1 is port ( RESET : in std_logic clk :
fpga_ads8364
- fpga控制ti的多通道高精度ad芯片ads8364的verilog源码-fpga multi-channel high-precision control ti ad-chip ads8364 the verilog source code
FSM
- 一种简单的状态机，本程序为初学者提供了一种编制状态机的框架。-a kind of simple FSM。
parallel2serial
- its code for converting parallel data into serial data stream.
lvbo
- 此程序基本上实现了数字滤波器的八位移位寄存器的功能。-This program is basically a digital filter to achieve the eight shift register function.