资源列表
alu8bit
- alu 8 bit using vhdl is very useful
diivider4
- 四位除法器，写的算法布扎带，想下就下，不下也行-Four divider, with a written calculation Fabu Zha, think the next on the next, no less will do
encoder_using_if.v
- this is a verilog code of encoder using if statement.
alu
- It is 32 bit ALU code in Verilog HDL programming Language
helu
- 多路逻辑信号-数字信号转换器。可根据此文件修改输入输出口数量。- Multiplexing logic signal- digital signal converter. The number of input and output ports can be modified according to this document.
circuit_timing
- verilog延时电路的不同写法，和综合能否。可对比学习-Different wording verilog delay circuit, and comprehensive ability. Comparable learning
buffer_tri_state
- Buffer tristate in vhdl
fenpin
- 基于50M分10K 1K 1000 100 10 1的分频，占空比 10/1-Based 50M min 10K 1K 1000 100 10 1 division, duty cycle 10/100
DEMUX
- Demultiplexor vhdl code
division1
- 基于vhdl/verilog的18位除法器程序。已经过仿真和综合。-Based on vhdl/verilog program for 18-bit divider. Has been simulation and synthesis.
asdasdasdasd
- 基于quartus的3-8译码器,可作为大型系统的译码器模块-Based on quartus a 3-8 decoder can be used as large-scale system decoder module
vhdl
- vhdl跑马灯 适合初学者同学...流水灯的制作-vhdl Marquee for beginner students to the production of light water ...