资源列表
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
c_create_a_stack_class_code
- c++创建栈类的程序代码，内容详细。是本人自己亲自编写，可以直接运用-c++ create a stack class code, and detailed. Written by me personally can be directly applied
VNOI_BONUS
- code spoj BONUS (oi)VNOI_BONUS.PAS(vn.spoj.pl)+ vali2.pas
sm
- 实验一_数字基带传输实验_实验单极性归零码的程序，欢迎指正-Experiment _ digital baseband transmission experiment _ experiment Unipolar NRZ program, please correct me
mix_map_ICA
- 程序将三副图象混合然后采用FastICA算法将其分离.通过ICA能将有用图像分离出来。-Program three mixed images and then be separated using FastICA algorithm.
math
- math.c是可用于在c语言中实现math文件的编程，也可在DSP开发中用于软件的仿真-The simulation is used to implement the programming math.c math files in c language, can also be used for software development in the DSP
NF2
- ARM系列 写入擦除读写功能的具体函数，有操作步骤-ARM series write erase read write function of the specific function, there are steps of operation
zf_2by2
- ZF linear detection scheme for wire less communication
TOP
- converting the given input image into pixel in vhdl
shengchengxinghao
- 产生随机信号。此模块是用于评估当信号中有谐波时，对电能质量产生的影响-Generate random signal.This module is used to assess when a harmonic signal, the influence on power quality
str_cpy.c
- 这是一个小程序，经过测试可以正常编译运行没有问题的！-This is a small program, its ok to compile and run. No problem is occurred
buildingszz
- 建立一个建筑物层次体系。 基类building派生住宅类house和办公类office-establish a system-level buildings. Derived base class residential building type house and office category office