资源列表
2-and-hex-output
- 汇编实现二进制和十六进制的输出，很久以前写的，具体看代码-Assembly realize binary and hexadecimal output
Find-the-even-minimum-value
- 用汇编实现寻找偶数中最小值，程序中事先给定偶数序列-Assembly language even find the lowest value in, program given a array for even
Character-classification
- 基于汇编的字符分类实现，将一个字符串中的字符、数字、等分行显示-Based on the character of assembly classification realized, will a string of characters, Numbers, and branch display
lexical-analyzer-CPP
- 通过设计编制调试一个具体的词法分析程序，加深对词法分析原理的理解。编译原理专用词法分析程序-Through the design of the preparation of debugging a lexical analysis of specific procedures, better understanding of the principles of the understanding of lexical analysis.
The.Art.of.Assembly.Language
- 汇编的艺术，计算机经典书籍，好好学习吧，共同努力，-The Art of Assembly Language
alarm-clock
- its a simple alarm clock source code which is written in assembly language-its a simple alarm clock source code which is written in assembly language....
sy4
- D74LS74 JK74ls112. LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY D74LS74 is port(clk,clr,PRE,D:in std_logic QT,QTN:out std_logic) end ENTITY D74LS74 architecture bhv of D74LS74 is signal q,qn:std_logic signal x:std_logic
sy1
- 28M分频器 D触发器 jk触发器 library ieee -library ieee use ieee.std_logic_1164.all use ieee.std_logic_arith.all use ieee.std_logic_unsigned.all entity ymq is port(num:in std_logic_vector(3 downto 0) dout:out std_logic_vect
1
- 加减计数器 library ieee use ieee. std_logic-_1164.all entity dec3_8 is port(a,b,c,s1,s2,s3: in std_logic y: out std_logic_vector(0 to 7)) end architecture b of dec3_8 is signal abc: std_logic_vector(0 t
mbr
- MBR登陆验证的汇编源码，带有详细注释。-The MBR login verification of assembly source code, with detailed annotations.
beibao
- 假设有一个能装入总体积为T的背包和n件体积分别为w1 , w2 , … , wn 的物品，能否从n件物品中挑选若干件恰好装满背包，即使w1 +w2 + … + wn=T，要求找出所有满足上述条件的解。例如：当T=10，各件物品的体积{1，8，4，3，5，2}时，可找到下列4组解： （1，4，3，2） （1，4，5） （8，2） （3，5，2）。 -Suppose there are a load of the backpack of the total volume of T
8086-instruction-system
- 这个文档详细讲述了8086CPU的指令系统-The document consits of the knowledge of 8086CPU instruction system