基于FPGA闹钟系统的设计。

1.秒模块实际上是一个计数器，一秒记录一次并输出。

2.分，时模块在一个脉冲上升沿计数一次的基础上，加入了时间调整控制。

3.调整时间的控制模块，在使能信号有效时，才可实现时分的调整。

4.闹钟调整及控制模块，可实现闹钟设时的调节功能。

5.显示模块，实现时间与闹钟显示的切换。

6.闹铃模块，实现闹铃的发声装置。

7.总逻辑模块，实现电子闹钟相应功能的总系统。

-FPGA-based alarm system design. 1. Second module is actually a counter, a second recording and output. 2. Am, when the module is a pulse based on the rising edge of a count by adding the time to adjust control. 3. Adjust the time of the control module, the enable signal is active in order to achieve the hours of adjustments. 4. Alarm clock adjustment and control modules can be realized when the alarm clock set up regulatory function. 5. Display module to realize the time and alarm clock display switch. 6. Alarm module to achieve the alarm audible signal devices. 7. The total logic block to realize the corresponding function of the total electronic alarm system.