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文件名称:Xilinx_ISE_FPGA

  • 所属分类：
    Linux-Unix program
  • 标签属性：
    [HTML]
  • 上传时间：
    2012-11-16
  • 文件大小：
    41.09mb
  • 已下载：
    0次
  • 提 供 者：
    THE****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

TRAININ xilinx ISE 11.1-TRAININ　xilinx ISE 11.1
相关搜索： ise xilinx ise Xilinx ISE 11.1 Xilinx ISE 11.1 ISE FPGA Xilinx 11.1

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Speedway/
Speedway/Fall_09/
Speedway/Fall_09/FPGA_Intro/
Speedway/Fall_09/FPGA_Intro/lab1/
Speedway/Fall_09/FPGA_Intro/lab1/sources/
Speedway/Fall_09/FPGA_Intro/lab1/sources/FPGA_Intro.ucf
Speedway/Fall_09/FPGA_Intro/lab1/vhdl/
Speedway/Fall_09/FPGA_Intro/lab1/vlog/
Speedway/Fall_09/FPGA_Intro/lab1_solution/
Speedway/Fall_09/FPGA_Intro/lab1_solution/sources/
Speedway/Fall_09/FPGA_Intro/lab1_solution/sources/FPGA_Intro.ucf
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/clocking.vhd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/clocking_arwz.ucf
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/FPGA_Intro_summary.html
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/fpga_intro.bgn
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/fpga_intro.bit
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.bld
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.cmd_log
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/fpga_intro.drc
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.lso
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.ncd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.ngc
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.ngd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.ngr
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.pad
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.par
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.pcf
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.prj
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.ptwx
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.stx
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.syr
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.twr
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.twx
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.ucf
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.unroutes
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.ut
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.vhd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.xpi
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro.xst
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_guide.ncd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_map.map
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_map.mrp
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_map.ncd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_map.ngm
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_map.xrpt
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_ngdbuild.xrpt
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_pad.csv
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_pad.txt
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_par.xrpt
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_prev_built.ngd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_summary.html
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_summary.xml
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_usage.xml
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_vhdl.prj
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/FPGA_Intro_xst.xrpt
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ipcore_dir/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj.gise
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj.ise
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj.ntrc_log
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj.xise
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/cst.xbcd
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/version
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/__OBJSTORE__/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/__OBJSTORE__/Autonym/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/__OBJSTORE__/common/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/
Speedway/Fall_09/FPGA_Intro/lab1_solution/vhdl/ISE_Proj/ISE_Proj_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProj

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