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文件名称:RD1030_demo

  • 所属分类：
    Other systems
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.68mb
  • 已下载：
    0次
  • 提 供 者：
    And***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

it is full lattice source code for implementation 7:1 interface for 4-5 differential input /outputs (like more fast interfaces)-it is full lattice　source code　for implementation 7:1 interface for 4-5 differential input /outputs (like more fast interfaces)　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
相关搜索： lattice code

(系统自动生成,下载前可以参看下载内容)

下载文件列表

RD1030_71LVDS_demo/Documents/
RD1030_71LVDS_demo/Documents/rd1030.pdf
RD1030_71LVDS_demo/ecp2/
RD1030_71LVDS_demo/ecp2/verilog/
RD1030_71LVDS_demo/ecp2/verilog/docs/
RD1030_71LVDS_demo/ecp2/verilog/par/
RD1030_71LVDS_demo/ecp2/verilog/par/loopback_par.lpf
RD1030_71LVDS_demo/ecp2/verilog/par/loopback_par.tcl
RD1030_71LVDS_demo/ecp2/verilog/par/loopback_par_tsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/par/video_par.lpf
RD1030_71LVDS_demo/ecp2/verilog/par/Video_par.tcl
RD1030_71LVDS_demo/ecp2/verilog/par/video_par_tsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/ReadMe.txt
RD1030_71LVDS_demo/ecp2/verilog/simulation/
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/rtl/
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/scripts/
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/scripts/loopback_fsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/scripts/loopback_tsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/scripts/video_fsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/scripts/video_tsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/timing/
RD1030_71LVDS_demo/ecp2/verilog/simulation/modelsim/timing/video_wave.do
RD1030_71LVDS_demo/ecp2/verilog/source/
RD1030_71LVDS_demo/ecp2/verilog/source/addsub8.v
RD1030_71LVDS_demo/ecp2/verilog/source/Add_8.v
RD1030_71LVDS_demo/ecp2/verilog/source/align_word.v
RD1030_71LVDS_demo/ecp2/verilog/source/asm.bat
RD1030_71LVDS_demo/ecp2/verilog/source/bit_align_ctl.v
RD1030_71LVDS_demo/ecp2/verilog/source/bit_align_ctl_sim.v
RD1030_71LVDS_demo/ecp2/verilog/source/CBHS.v
RD1030_71LVDS_demo/ecp2/verilog/source/CBHS_adj.v
RD1030_71LVDS_demo/ecp2/verilog/source/Char_Gen.mem
RD1030_71LVDS_demo/ecp2/verilog/source/Char_Gen.v
RD1030_71LVDS_demo/ecp2/verilog/source/CSC1.v
RD1030_71LVDS_demo/ecp2/verilog/source/CSC2.v
RD1030_71LVDS_demo/ecp2/verilog/source/deserializer.v
RD1030_71LVDS_demo/ecp2/verilog/source/deserializer_fsm.v
RD1030_71LVDS_demo/ecp2/verilog/source/dpram16x8.v
RD1030_71LVDS_demo/ecp2/verilog/source/dpram32x8.v
RD1030_71LVDS_demo/ecp2/verilog/source/isp8asm.exe
RD1030_71LVDS_demo/ecp2/verilog/source/isp8_cfg.v
RD1030_71LVDS_demo/ecp2/verilog/source/isp8_main.v
RD1030_71LVDS_demo/ecp2/verilog/source/isp8_prom.lpc
RD1030_71LVDS_demo/ecp2/verilog/source/isp8_prom.v
RD1030_71LVDS_demo/ecp2/verilog/source/Loopback_Demo_7_to_1_LVDS_TOP.v
RD1030_71LVDS_demo/ecp2/verilog/source/lvds_7_to_1_def.v
RD1030_71LVDS_demo/ecp2/verilog/source/LVDS_7_to_1_RX.v
RD1030_71LVDS_demo/ecp2/verilog/source/LVDS_7_to_1_RX_sim.v
RD1030_71LVDS_demo/ecp2/verilog/source/LVDS_7_to_1_TX.v
RD1030_71LVDS_demo/ecp2/verilog/source/LVDS_7_to_1_TX_cd.v
RD1030_71LVDS_demo/ecp2/verilog/source/Mico8_OSD.lst
RD1030_71LVDS_demo/ecp2/verilog/source/Mico8_OSD.mem
RD1030_71LVDS_demo/ecp2/verilog/source/Mico8_OSD.s
RD1030_71LVDS_demo/ecp2/verilog/source/MULT_9X9_DYN_SAUB.v
RD1030_71LVDS_demo/ecp2/verilog/source/MULT_9X9_UASB.v
RD1030_71LVDS_demo/ecp2/verilog/source/MULT_9X9_UAUB.v
RD1030_71LVDS_demo/ecp2/verilog/source/Opaque_adj.v
RD1030_71LVDS_demo/ecp2/verilog/source/OSD.v
RD1030_71LVDS_demo/ecp2/verilog/source/OSD_text.v
RD1030_71LVDS_demo/ecp2/verilog/source/OSD_text_code.mem
RD1030_71LVDS_demo/ecp2/verilog/source/OSD_text_code.v
RD1030_71LVDS_demo/ecp2/verilog/source/OSD_text_color.mem
RD1030_71LVDS_demo/ecp2/verilog/source/OSD_text_color.v
RD1030_71LVDS_demo/ecp2/verilog/source/ReadMe.txt
RD1030_71LVDS_demo/ecp2/verilog/source/RGB_adj.v
RD1030_71LVDS_demo/ecp2/verilog/source/RGB_gain.v
RD1030_71LVDS_demo/ecp2/verilog/source/rxpll.lpc
RD1030_71LVDS_demo/ecp2/verilog/source/rxpll.v
RD1030_71LVDS_demo/ecp2/verilog/source/rx_iddr_x2_mod.v
RD1030_71LVDS_demo/ecp2/verilog/source/serializer.v
RD1030_71LVDS_demo/ecp2/verilog/source/serializer_fsm.v
RD1030_71LVDS_demo/ecp2/verilog/source/serializer_txclk.v
RD1030_71LVDS_demo/ecp2/verilog/source/sin_cos.tcl
RD1030_71LVDS_demo/ecp2/verilog/source/SIN_COS_ROM.mem
RD1030_71LVDS_demo/ecp2/verilog/source/SIN_COS_ROM.v
RD1030_71LVDS_demo/ecp2/verilog/source/spram16x10.v
RD1030_71LVDS_demo/ecp2/verilog/source/spram16x11.v
RD1030_71LVDS_demo/ecp2/verilog/source/spram16x12.v
RD1030_71LVDS_demo/ecp2/verilog/source/spram16x8.v
RD1030_71LVDS_demo/ecp2/verilog/source/spram16x9.v
RD1030_71LVDS_demo/ecp2/verilog/source/spram32x8.v
RD1030_71LVDS_demo/ecp2/verilog/source/Sub_11.v
RD1030_71LVDS_demo/ecp2/verilog/source/Sub_9.v
RD1030_71LVDS_demo/ecp2/verilog/source/txpll.lpc
RD1030_71LVDS_demo/ecp2/verilog/source/txpll.v
RD1030_71LVDS_demo/ecp2/verilog/source/tx_oddr_x2_mod.v
RD1030_71LVDS_demo/ecp2/verilog/source/Video_Demo_7_to_1_LVDS_TOP.v
RD1030_71LVDS_demo/ecp2/verilog/source/word_align_ctl.v
RD1030_71LVDS_demo/ecp2/verilog/synthesis/
RD1030_71LVDS_demo/ecp2/verilog/synthesis/loopback_syn.tcl
RD1030_71LVDS_demo/ecp2/verilog/synthesis/loopback_syn_tsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/synthesis/video_syn.tcl
RD1030_71LVDS_demo/ecp2/verilog/synthesis/video_syn_tsim.tcl
RD1030_71LVDS_demo/ecp2/verilog/testbench/
RD1030_71LVDS_demo/ecp2/verilog/testbench/Loopback_Demo_7_to_1_LVDS_TOP_TB.v
RD1030_71LVDS_demo/ecp2/v

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