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文件名称:VLSI_CA1.tar

  • 所属分类：
    Other systems
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    144.12kb
  • 已下载：
    0次
  • 提 供 者：
    met****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

this the implementaion of an 8-bit mirror adder in Verilog-this is the implementaion of an 8-bit mirror adder in Verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VLSI_CA1/
VLSI_CA1/p1_a/
VLSI_CA1/p1_a/schematic/
VLSI_CA1/p1_a/schematic/master.tag
VLSI_CA1/p1_a/schematic/pc.db
VLSI_CA1/p1_a/schematic/sch.cd%
VLSI_CA1/p1_a/schematic/sch.cd-
VLSI_CA1/p1_a/schematic/sch.cdb
VLSI_CA1/p1_a/schematic/prop.xx
VLSI_CA1/p1_a/layout/
VLSI_CA1/p1_a/layout/master.tag
VLSI_CA1/p1_a/layout/pc.db
VLSI_CA1/p1_a/layout/layout.cd%
VLSI_CA1/p1_a/layout/layout.cdb
VLSI_CA1/p1_a/av_extracted/
VLSI_CA1/p1_a/av_extracted/master.tag
VLSI_CA1/p1_a/av_extracted/pc.db
VLSI_CA1/p1_a/av_extracted/layout.cdb
VLSI_CA1/p1_a/av_extracted/prop.xx
VLSI_CA1/p1_a/symbol/
VLSI_CA1/p1_a/symbol/master.tag
VLSI_CA1/p1_a/symbol/pc.db
VLSI_CA1/p1_a/symbol/symbol.cd%
VLSI_CA1/p1_a/symbol/symbol.cdb
VLSI_CA1/p1_a/prop.xx
VLSI_CA1/p1_d/
VLSI_CA1/p1_d/schematic/
VLSI_CA1/p1_d/schematic/master.tag
VLSI_CA1/p1_d/schematic/pc.db
VLSI_CA1/p1_d/schematic/sch.cd%
VLSI_CA1/p1_d/schematic/sch.cdb
VLSI_CA1/p1_d/schematic/prop.xx
VLSI_CA1/p1_e/
VLSI_CA1/p1_e/schematic/
VLSI_CA1/p1_e/schematic/master.tag
VLSI_CA1/p1_e/schematic/pc.db
VLSI_CA1/p1_e/schematic/sch.cd%
VLSI_CA1/p1_e/schematic/sch.cdb
VLSI_CA1/p1_e/schematic/prop.xx
VLSI_CA1/p1_f/
VLSI_CA1/p1_f/schematic/
VLSI_CA1/p1_f/schematic/master.tag
VLSI_CA1/p1_f/schematic/pc.db
VLSI_CA1/p1_f/schematic/sch.cd%
VLSI_CA1/p1_f/schematic/sch.cdb
VLSI_CA1/p1_f/schematic/prop.xx
VLSI_CA1/p2_a/
VLSI_CA1/p2_a/schematic/
VLSI_CA1/p2_a/schematic/master.tag
VLSI_CA1/p2_a/schematic/pc.db
VLSI_CA1/p2_a/schematic/sch.cd%
VLSI_CA1/p2_a/schematic/sch.cdb
VLSI_CA1/p2_a/schematic/prop.xx
VLSI_CA1/p2_a/layout/
VLSI_CA1/p2_a/layout/master.tag
VLSI_CA1/p2_a/layout/pc.db
VLSI_CA1/p2_a/layout/layout.cd%
VLSI_CA1/p2_a/layout/layout.cdb
VLSI_CA1/p2_a/av_extracted/
VLSI_CA1/p2_a/av_extracted/master.tag
VLSI_CA1/p2_a/av_extracted/pc.db
VLSI_CA1/p2_a/av_extracted/layout.cdb
VLSI_CA1/p2_a/av_extracted/prop.xx
VLSI_CA1/p2_a/symbol/
VLSI_CA1/p2_a/symbol/master.tag
VLSI_CA1/p2_a/symbol/pc.db
VLSI_CA1/p2_a/symbol/symbol.cd%
VLSI_CA1/p2_a/symbol/symbol.cdb
VLSI_CA1/p2_a/prop.xx
VLSI_CA1/p3_a/
VLSI_CA1/p3_a/schematic/
VLSI_CA1/p3_a/schematic/master.tag
VLSI_CA1/p3_a/schematic/pc.db
VLSI_CA1/p3_a/schematic/sch.cd%
VLSI_CA1/p3_a/schematic/sch.cdb
VLSI_CA1/p3_a/schematic/prop.xx
VLSI_CA1/p3_a/layout/
VLSI_CA1/p3_a/layout/master.tag
VLSI_CA1/p3_a/layout/pc.db
VLSI_CA1/p3_a/layout/layout.cd%
VLSI_CA1/p3_a/layout/layout.cdb
VLSI_CA1/p3_a/av_extracted/
VLSI_CA1/p3_a/av_extracted/master.tag
VLSI_CA1/p3_a/av_extracted/layout.cdb
VLSI_CA1/p3_a/symbol/
VLSI_CA1/p3_a/symbol/master.tag
VLSI_CA1/p3_a/symbol/pc.db
VLSI_CA1/p3_a/symbol/symbol.cd%
VLSI_CA1/p3_a/symbol/symbol.cdb
VLSI_CA1/p3_a/prop.xx
VLSI_CA1/p4_a/
VLSI_CA1/p4_a/schematic/
VLSI_CA1/p4_a/schematic/master.tag
VLSI_CA1/p4_a/schematic/pc.db
VLSI_CA1/p4_a/schematic/sch.cd%
VLSI_CA1/p4_a/schematic/sch.cdb
VLSI_CA1/p4_a/schematic/sch.cdb.cdslck
VLSI_CA1/p4_a/schematic/prop.xx
VLSI_CA1/p4_a/layout/
VLSI_CA1/p4_a/layout/master.tag
VLSI_CA1/p4_a/layout/pc.db
VLSI_CA1/p4_a/layout/layout.cdb.cdslck
VLSI_CA1/p4_a/layout/layout.cd%
VLSI_CA1/p4_a/layout/layout.cd-
VLSI_CA1/p4_a/layout/layout.cdb
VLSI_CA1/p4_a/av_extracted/
VLSI_CA1/p4_a/av_extracted/master.tag
VLSI_CA1/p4_a/av_extracted/pc.db
VLSI_CA1/p4_a/av_extracted/layout.cdb
VLSI_CA1/p4_a/av_extracted/prop.xx
VLSI_CA1/p4_a/symbol/
VLSI_CA1/p4_a/symbol/master.tag
VLSI_CA1/p4_a/symbol/pc.db
VLSI_CA1/p4_a/symbol/symbol.cd%
VLSI_CA1/p4_a/symbol/symbol.cdb
VLSI_CA1/p4_a/prop.xx
VLSI_CA1/p4_b/
VLSI_CA1/p4_b/schematic/
VLSI_CA1/p4_b/schematic/master.tag
VLSI_CA1/p4_b/schematic/pc.db
VLSI_CA1/p4_b/schematic/sch.cd%
VLSI_CA1/p4_b/schematic/sch.cdb
VLSI_CA1/p4_b/schematic/prop.xx
VLSI_CA1/p4_b/layout/
VLSI_CA1/p4_b/layout/master.tag
VLSI_CA1/p4_b/layout/pc.db
VLSI_CA1/p4_b/layout/layout.cdb.cdslck
VLSI_CA1/p4_b/layout/layout.cd%
VLSI_CA1/p4_b/layout/layout.cdb
VLSI_CA1/p4_b/symbol/
VLSI_CA1/p4_b/symbol/master.tag
VLSI_CA1/p4_b/symbol/pc.db
VLSI_CA1/p4_b/symbol/symbol.cd%
VLSI_CA1/p4_b/symbol/symbol.cdb
VLSI_CA1/p4_b/prop.xx
VLSI_CA1/temp/
VLSI_CA1/temp/layout/
VLSI_CA1/temp/layout/master.tag
VLSI_CA1/temp/layout/pc.db
VLSI_CA1/temp/layout/layout.cd%
VLSI_CA1/temp/layout/layout.cdb
VLSI_CA1/p1_a_tb/
VLSI_CA1/p1_a_tb/schematic/
VLSI_CA1/p1_a_tb/schematic/master.tag
VLSI_CA1/p1_a_tb/schematic/pc.db
VLSI_CA1/p1_a_tb/schematic/sch.cd%
VLSI_CA1/p1_a_tb/schematic/sch.cdb
VLSI_CA1/p1_a_tb/schematic/prop.xx
VLSI_CA1/p1_a_tb/config/
VLSI_CA1/p1_a_tb/config/master.tag
VLSI_CA1/p1_a_tb/config/expand.cfg%
VLSI_CA1/p1_a_tb/config/expand.cfg
VLSI_CA1/p2_a_tb/
VLSI_CA1/p2_a_tb/schematic/
VLSI_CA1/p2_a_tb/schematic/master.tag
VLSI_CA1/p2_a_tb/schematic/pc.db
VLSI_CA1/p2_a_tb/schematic/sch.cd%
VLSI_CA1/p2_a_tb/schematic/sch.cdb
VLSI_CA1/p2_a_tb/schematic/prop.xx
VLSI_CA1/p3_a_tb/
VLSI_CA1/p3_a_tb/schematic/
VLSI_CA1/p3_a_tb/schematic/master.tag
VLSI_CA1/p3_a_tb/schematic/pc.db
VLSI_CA1/p3_a_tb/schematic/sch.cd%
VLSI_CA1/p3_a_tb/schematic/sch.cdb
VLSI_CA1/p3_a_tb/schematic/prop.xx
VLSI_CA1/p4_b_tb/
VLSI_CA1/p4_b_tb/schematic/
VLSI_CA1/p4_b_tb/schematic/master.tag
VLSI_CA1/p4_b_tb/schematic/pc.db
VLSI_CA1/p4_b_tb/schematic/sch.cd%
VLSI_CA1/p4_b_tb/schematic/sch.c

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