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文件名称:LCD12864

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  • 上传时间:
    2012-11-16
  • 文件大小:
    4.84mb
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    0次
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介绍说明--下载内容来自于网络,使用问题请自行百度

12864显示驱动FPGA VERILOG -12864 display driver
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LCD12864/
LCD12864/db/
LCD12864/db/LCD12864.(0).cnf.cdb
LCD12864/db/LCD12864.(0).cnf.hdb
LCD12864/db/LCD12864.ace_cmp.cdb
LCD12864/db/LCD12864.ace_cmp.hdb
LCD12864/db/LCD12864.asm.qmsg
LCD12864/db/LCD12864.asm.rdb
LCD12864/db/LCD12864.asm_labs.ddb
LCD12864/db/LCD12864.cbx.xml
LCD12864/db/LCD12864.cmp.cdb
LCD12864/db/LCD12864.cmp.hdb
LCD12864/db/LCD12864.cmp.kpt
LCD12864/db/LCD12864.cmp.logdb
LCD12864/db/LCD12864.cmp.rdb
LCD12864/db/LCD12864.cmp.tdb
LCD12864/db/LCD12864.cmp0.ddb
LCD12864/db/LCD12864.cmp2.ddb
LCD12864/db/LCD12864.db_info
LCD12864/db/LCD12864.eco.cdb
LCD12864/db/LCD12864.eda.qmsg
LCD12864/db/LCD12864.eds_overflow
LCD12864/db/LCD12864.fit.qmsg
LCD12864/db/LCD12864.fnsim.hdb
LCD12864/db/LCD12864.fnsim.qmsg
LCD12864/db/LCD12864.hier_info
LCD12864/db/LCD12864.hif
LCD12864/db/LCD12864.lpc.html
LCD12864/db/LCD12864.lpc.rdb
LCD12864/db/LCD12864.lpc.txt
LCD12864/db/LCD12864.map.cdb
LCD12864/db/LCD12864.map.hdb
LCD12864/db/LCD12864.map.logdb
LCD12864/db/LCD12864.map.qmsg
LCD12864/db/LCD12864.pre_map.cdb
LCD12864/db/LCD12864.pre_map.hdb
LCD12864/db/LCD12864.rtlv.hdb
LCD12864/db/LCD12864.rtlv_sg.cdb
LCD12864/db/LCD12864.rtlv_sg_swap.cdb
LCD12864/db/LCD12864.sgdiff.cdb
LCD12864/db/LCD12864.sgdiff.hdb
LCD12864/db/LCD12864.sim.cvwf
LCD12864/db/LCD12864.sim.hdb
LCD12864/db/LCD12864.sim.qmsg
LCD12864/db/LCD12864.sim.rdb
LCD12864/db/LCD12864.simfam
LCD12864/db/LCD12864.sld_design_entry.sci
LCD12864/db/LCD12864.sld_design_entry_dsc.sci
LCD12864/db/LCD12864.smart_action.txt
LCD12864/db/LCD12864.smp_dump.txt
LCD12864/db/LCD12864.sta.qmsg
LCD12864/db/LCD12864.syn_hier_info
LCD12864/db/LCD12864.tan.qmsg
LCD12864/db/LCD12864.tis_db_list.ddb
LCD12864/db/LCD12864.tmw_info
LCD12864/db/logic_util_heursitic.dat
LCD12864/db/prev_cmp_LCD12864.asm.qmsg
LCD12864/db/prev_cmp_LCD12864.eda.qmsg
LCD12864/db/prev_cmp_LCD12864.fit.qmsg
LCD12864/db/prev_cmp_LCD12864.map.qmsg
LCD12864/db/prev_cmp_LCD12864.qmsg
LCD12864/db/prev_cmp_LCD12864.sim.qmsg
LCD12864/db/prev_cmp_LCD12864.tan.qmsg
LCD12864/db/wed.wsf
LCD12864/incremental_db/
LCD12864/incremental_db/compiled_partitions/
LCD12864/incremental_db/compiled_partitions/LCD12864.root_partition.map.kpt
LCD12864/incremental_db/README
LCD12864/LCD12864.asm.rpt
LCD12864/LCD12864.cdf
LCD12864/LCD12864.done
LCD12864/LCD12864.dpf
LCD12864/LCD12864.eda.rpt
LCD12864/LCD12864.fit.rpt
LCD12864/LCD12864.fit.smsg
LCD12864/LCD12864.fit.summary
LCD12864/LCD12864.flow.rpt
LCD12864/LCD12864.map.rpt
LCD12864/LCD12864.map.smsg
LCD12864/LCD12864.map.summary
LCD12864/LCD12864.pin
LCD12864/LCD12864.pof
LCD12864/LCD12864.qpf
LCD12864/LCD12864.qsf
LCD12864/LCD12864.sdc
LCD12864/LCD12864.sim.rpt
LCD12864/LCD12864.sof
LCD12864/LCD12864.tan.rpt
LCD12864/LCD12864.tan.summary
LCD12864/LCD12864.v
LCD12864/LCD12864.v.bak
LCD12864/LCD12864.vwf
LCD12864/LCD12864_assignment_defaults.qdf
LCD12864/LCD12864_nativelink_simulation.rpt
LCD12864/simulation/
LCD12864/simulation/modelsim/
LCD12864/simulation/modelsim/LCD12864.sft
LCD12864/simulation/modelsim/LCD12864.vo
LCD12864/simulation/modelsim/LCD12864.vt
LCD12864/simulation/modelsim/LCD12864.vt.bak
LCD12864/simulation/modelsim/LCD12864_modelsim.xrf
LCD12864/simulation/modelsim/LCD12864_run_msim_gate_verilog.do
LCD12864/simulation/modelsim/LCD12864_run_msim_rtl_verilog.do
LCD12864/simulation/modelsim/LCD12864_run_msim_rtl_verilog.do.bak
LCD12864/simulation/modelsim/LCD12864_run_msim_rtl_verilog.do.bak1
LCD12864/simulation/modelsim/LCD12864_run_msim_rtl_verilog.do.bak2
LCD12864/simulation/modelsim/LCD12864_v.sdo
LCD12864/simulation/modelsim/msim_transcript
LCD12864/simulation/modelsim/rtl_work/
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864/
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864/verilog.asm
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864/_primary.dat
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864/_primary.vhd
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864_vlg_tst/
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864_vlg_tst/verilog.asm
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864_vlg_tst/_primary.dat
LCD12864/simulation/modelsim/rtl_work/@l@c@d12864_vlg_tst/_primary.vhd
LCD12864/simulation/modelsim/rtl_work/_info
LCD12864/simulation/modelsim/verilog_libs/
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
LCD12864/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@

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