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文件名称:uart-IP-Core

  • 所属分类：
    Com Port
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    314.52kb
  • 已下载：
    1次
  • 提 供 者：
    吴***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart IP Core/
uart IP Core/bench/
uart IP Core/bench/CVS/
uart IP Core/bench/CVS/Entries
uart IP Core/bench/CVS/Repository
uart IP Core/bench/CVS/Root
uart IP Core/bench/verilog/
uart IP Core/bench/verilog/CVS/
uart IP Core/bench/verilog/CVS/Entries
uart IP Core/bench/verilog/CVS/Repository
uart IP Core/bench/verilog/CVS/Root
uart IP Core/bench/verilog/readme.txt
uart IP Core/bench/verilog/test_cases/
uart IP Core/bench/verilog/test_cases/CVS/
uart IP Core/bench/verilog/test_cases/CVS/Entries
uart IP Core/bench/verilog/test_cases/CVS/Repository
uart IP Core/bench/verilog/test_cases/CVS/Root
uart IP Core/bench/verilog/test_cases/uart_int.v
uart IP Core/bench/verilog/uart_device.v
uart IP Core/bench/verilog/uart_device_utilities.v
uart IP Core/bench/verilog/uart_log.v
uart IP Core/bench/verilog/uart_test.v
uart IP Core/bench/verilog/uart_testbench.v
uart IP Core/bench/verilog/uart_testbench_defines.v
uart IP Core/bench/verilog/uart_testbench_utilities.v
uart IP Core/bench/verilog/uart_wb_utilities.v
uart IP Core/bench/verilog/vapi.log
uart IP Core/bench/verilog/wb_mast.v
uart IP Core/bench/verilog/wb_master_model.v
uart IP Core/bench/verilog/wb_model_defines.v
uart IP Core/bench/vhdl/
uart IP Core/bench/vhdl/.keepme
uart IP Core/bench/vhdl/CVS/
uart IP Core/bench/vhdl/CVS/Entries
uart IP Core/bench/vhdl/CVS/Repository
uart IP Core/bench/vhdl/CVS/Root
uart IP Core/CVS/
uart IP Core/CVS/Entries
uart IP Core/CVS/Repository
uart IP Core/CVS/Root
uart IP Core/Doc/
uart IP Core/Doc/CHANGES.txt
uart IP Core/Doc/CVS/
uart IP Core/Doc/CVS/Entries
uart IP Core/Doc/CVS/Repository
uart IP Core/Doc/CVS/Root
uart IP Core/Doc/src/
uart IP Core/Doc/src/CVS/
uart IP Core/Doc/src/CVS/Entries
uart IP Core/Doc/src/CVS/Repository
uart IP Core/Doc/src/CVS/Root
uart IP Core/Doc/src/UART_spec.doc
uart IP Core/Doc/UART_spec.pdf
uart IP Core/fv/
uart IP Core/fv/.keepme
uart IP Core/fv/CVS/
uart IP Core/fv/CVS/Entries
uart IP Core/fv/CVS/Repository
uart IP Core/fv/CVS/Root
uart IP Core/lint/
uart IP Core/lint/bin/
uart IP Core/lint/bin/.keepme
uart IP Core/lint/bin/CVS/
uart IP Core/lint/bin/CVS/Entries
uart IP Core/lint/bin/CVS/Repository
uart IP Core/lint/bin/CVS/Root
uart IP Core/lint/CVS/
uart IP Core/lint/CVS/Entries
uart IP Core/lint/CVS/Repository
uart IP Core/lint/CVS/Root
uart IP Core/lint/log/
uart IP Core/lint/log/.keepme
uart IP Core/lint/log/CVS/
uart IP Core/lint/log/CVS/Entries
uart IP Core/lint/log/CVS/Repository
uart IP Core/lint/log/CVS/Root
uart IP Core/lint/out/
uart IP Core/lint/out/.keepme
uart IP Core/lint/out/CVS/
uart IP Core/lint/out/CVS/Entries
uart IP Core/lint/out/CVS/Repository
uart IP Core/lint/out/CVS/Root
uart IP Core/lint/run/
uart IP Core/lint/run/.keepme
uart IP Core/lint/run/CVS/
uart IP Core/lint/run/CVS/Entries
uart IP Core/lint/run/CVS/Repository
uart IP Core/lint/run/CVS/Root
uart IP Core/rtl/
uart IP Core/rtl/CVS/
uart IP Core/rtl/CVS/Entries
uart IP Core/rtl/CVS/Repository
uart IP Core/rtl/CVS/Root
uart IP Core/rtl/verilog/
uart IP Core/rtl/verilog-backup/
uart IP Core/rtl/verilog-backup/CVS/
uart IP Core/rtl/verilog-backup/CVS/Entries
uart IP Core/rtl/verilog-backup/CVS/Repository
uart IP Core/rtl/verilog-backup/CVS/Root
uart IP Core/rtl/verilog-backup/timescale.v
uart IP Core/rtl/verilog-backup/uart_defines.v
uart IP Core/rtl/verilog-backup/uart_fifo.v
uart IP Core/rtl/verilog-backup/uart_receiver.v
uart IP Core/rtl/verilog-backup/uart_regs.v
uart IP Core/rtl/verilog-backup/uart_top.v
uart IP Core/rtl/verilog-backup/uart_transmitter.v
uart IP Core/rtl/verilog-backup/uart_wb.v
uart IP Core/rtl/verilog/CVS/
uart IP Core/rtl/verilog/CVS/Entries
uart IP Core/rtl/verilog/CVS/Repository
uart IP Core/rtl/verilog/CVS/Root
uart IP Core/rtl/verilog/raminfr.v
uart IP Core/rtl/verilog/timescale.v
uart IP Core/rtl/verilog/uart_debug_if.v
uart IP Core/rtl/verilog/uart_defines.v
uart IP Core/rtl/verilog/uart_receiver.v
uart IP Core/rtl/verilog/uart_regs.v
uart IP Core/rtl/verilog/uart_rfifo.v
uart IP Core/rtl/verilog/uart_sync_flops.v
uart IP Core/rtl/verilog/uart_tfifo.v
uart IP Core/rtl/verilog/uart_top.v
uart IP Core/rtl/verilog/uart_transmitter.v
uart IP Core/rtl/verilog/uart_wb.v
uart IP Core/rtl/vhdl/
uart IP Core/rtl/vhdl/.keepme
uart IP Core/rtl/vhdl/CVS/
uart IP Core/rtl/vhdl/CVS/Entries
uart IP Core/rtl/vhdl/CVS/Repository
uart IP Core/rtl/vhdl/CVS/Root
uart IP Core/sim/
uart IP Core/sim/CVS/
uart IP Core/sim/CVS/Entries
uart IP Core/sim/CVS/Repository
uart IP Core/sim/CVS/Root
uart IP Core/sim/gate_sim/
uart IP Core/sim/gate_sim/bin/
uart IP Core/sim/gate_sim/bin/.keepme
uart IP Core/sim/gate_sim/bin/CVS/
uart IP Core/sim/gate_sim/bin/CVS/Entries
uart IP Core/sim/gate_sim/bin/CVS/Repository
uart IP Core/sim/gate_sim/bin/CVS/Root
uart IP Core/sim/gate_sim/CVS/
uart IP Core/sim/gate_sim/CVS/Entries
uart IP Core/sim/gate_sim/CVS/Repository
uart IP Core/sim/gate_sim/CVS/Root
uart IP Core/sim/gate_sim/log/
uart IP Core/sim/gate_sim/log/.keepme
uart IP Core/sim/gate_sim/log/CVS/
uart IP Core/sim/gate_sim/log/CVS/Entries
uart IP Core/sim/gate_sim/log/CVS/Repository
uart IP Core/sim/gate_sim/log/CVS/Root
uart IP Core/sim

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