example1_aldec/
example1_aldec/code_conv_2processes.vhd
example1_aldec/README.txt
example1_aldec/shift_register.vhd
example1_aldec/testbench_top_level.vhd
example1_aldec/top_level.vhd
example1_ise/
example1_ise/ck_divider.vhd
example1_ise/code_conv_2processes.vhd
example1_ise/shift_register.vhd
example1_ise/top_level.ucf
example1_ise/top_level.vhd
example2/
example2/implementation_A/
example2/implementation_A/fsmd.pdf
example2/implementation_A/top_level_bit_diff_impl_A.vhd
example2/implementation_B/
example2/implementation_B/add.vhd
example2/implementation_B/comp.vhd
example2/implementation_B/datapath.pdf
example2/implementation_B/datapath.vhd
example2/implementation_B/fsm.vhd
example2/implementation_B/fsmd.pdf
example2/implementation_B/mux2x1.vhd
example2/implementation_B/reg.vhd
example2/implementation_B/sub.vhd
example2/implementation_B/top_level.vhd
example2/implementation_B/top_level_bit_diff_impl_B.vhd
example2/README.txt
lab4_FSM.pdf