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文件名称:ethmac10_100M

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    2013-03-16
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    18.05mb
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以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of

the Ethernet standard. It is designed to run

according to the IEEE 802.3 and 802.3u

specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
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下载文件列表

ethmac/branches/unneback/bench/verilog/eth_host.v
ethmac/branches/unneback/bench/verilog/eth_memory.v
ethmac/branches/unneback/bench/verilog/eth_phy.v
ethmac/branches/unneback/bench/verilog/eth_phy_defines.v
ethmac/branches/unneback/bench/verilog/tb_cop.v
ethmac/branches/unneback/bench/verilog/tb_ethernet.v
ethmac/branches/unneback/bench/verilog/tb_ethernet_with_cop.v
ethmac/branches/unneback/bench/verilog/tb_eth_defines.v
ethmac/branches/unneback/bench/verilog/tb_eth_top.v
ethmac/branches/unneback/bench/verilog/wb_bus_mon.v
ethmac/branches/unneback/bench/verilog/wb_master32.v
ethmac/branches/unneback/bench/verilog/wb_master_behavioral.v
ethmac/branches/unneback/bench/verilog/wb_model_defines.v
ethmac/branches/unneback/bench/verilog/wb_slave_behavioral.v
ethmac/branches/unneback/doc/ethernet_datasheet_OC_head.pdf
ethmac/branches/unneback/doc/ethernet_product_brief_OC_head.pdf
ethmac/branches/unneback/doc/eth_design_document.pdf
ethmac/branches/unneback/doc/eth_speci.pdf
ethmac/branches/unneback/doc/src/ethernet_datasheet_OC_head.doc
ethmac/branches/unneback/doc/src/ethernet_product_brief_OC_head.doc
ethmac/branches/unneback/doc/src/eth_design_document.doc
ethmac/branches/unneback/doc/src/eth_speci.doc
ethmac/branches/unneback/Makefile
ethmac/branches/unneback/README.txt
ethmac/branches/unneback/rtl/verilog/BUGS
ethmac/branches/unneback/rtl/verilog/eth_clockgen.v
ethmac/branches/unneback/rtl/verilog/eth_cop.v
ethmac/branches/unneback/rtl/verilog/eth_crc.v
ethmac/branches/unneback/rtl/verilog/eth_defines.v
ethmac/branches/unneback/rtl/verilog/eth_fifo.v
ethmac/branches/unneback/rtl/verilog/eth_maccontrol.v
ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
ethmac/branches/unneback/rtl/verilog/eth_miim.v
ethmac/branches/unneback/rtl/verilog/eth_outputcontrol.v
ethmac/branches/unneback/rtl/verilog/eth_random.v
ethmac/branches/unneback/rtl/verilog/eth_receivecontrol.v
ethmac/branches/unneback/rtl/verilog/eth_register.v
ethmac/branches/unneback/rtl/verilog/eth_registers.v
ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
ethmac/branches/unneback/rtl/verilog/eth_rxcounters.v
ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
ethmac/branches/unneback/rtl/verilog/eth_rxstatem.v
ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
ethmac/branches/unneback/rtl/verilog/eth_spram_256x32.v
ethmac/branches/unneback/rtl/verilog/eth_top.v
ethmac/branches/unneback/rtl/verilog/eth_transmitcontrol.v
ethmac/branches/unneback/rtl/verilog/eth_txcounters.v
ethmac/branches/unneback/rtl/verilog/eth_txethmac.v
ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
ethmac/branches/unneback/rtl/verilog/Makefile
ethmac/branches/unneback/rtl/verilog/timescale.v
ethmac/branches/unneback/rtl/verilog/TODO
ethmac/branches/unneback/rtl/verilog/xilinx_dist_ram_16x32.v
ethmac/branches/unneback/scripts/icarus.scr
ethmac/branches/unneback/scripts/Makefile
ethmac/branches/unneback/sim/rtl_sim/bin/artisan_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/bin/cds.lib
ethmac/branches/unneback/sim/rtl_sim/bin/hdl.var
ethmac/branches/unneback/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
ethmac/branches/unneback/sim/rtl_sim/bin/ncelab.args
ethmac/branches/unneback/sim/rtl_sim/bin/ncelab_xilinx.args
ethmac/branches/unneback/sim/rtl_sim/bin/ncsim.rc
ethmac/branches/unneback/sim/rtl_sim/bin/ncsim_waves.rc
ethmac/branches/unneback/sim/rtl_sim/bin/rtl_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/bin/run_sim
ethmac/branches/unneback/sim/rtl_sim/bin/sim_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/bin/xilinx_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/log/dir_keeper
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/bin/do.do
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/bin/eth_wave.do
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/bin/vlog.opt
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/bin/work/dir.keeper
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/bin/work/_info
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/log/dir.keeper
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/out/dir.keeper
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/run/dir.keeper
ethmac/branches/unneback/sim/rtl_sim/modelsim_sim/run/tb_eth.do
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/artisan_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/cds.lib
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/hdl.var
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/INCA_libs/worklib/dir_keeper
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/ncelab.args
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/ncelab_xilinx.args
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/ncsim.rc
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/ncsim_waves.rc
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/rtl_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/sim_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/vs_file_list.lst
ethmac/branches/unneback/sim/rtl_sim/ncsim_sim/bin/xilinx_file_list.lst
ethmac/

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