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文件名称:i2c-verilog-vhdl

  • 所属分类：
    WinSock-NDIS
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2013-05-15
  • 文件大小：
    663.13kb
  • 已下载：
    0次
  • 提 供 者：
    xum***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

I2C总线VHDL/Verilog HDL源码

通过仿真验证正确，希望对大家有用-I2C bus VHDL/Verilog HDL source code is verified by simulation is correct, we hope to useful
(系统自动生成,下载前可以参看下载内容)

下载文件列表

i2c verilog vhdl/
i2c verilog vhdl/CVS/
i2c verilog vhdl/CVS/Entries
i2c verilog vhdl/CVS/Repository
i2c verilog vhdl/CVS/Root
i2c verilog vhdl/bench/
i2c verilog vhdl/bench/CVS/
i2c verilog vhdl/bench/CVS/Entries
i2c verilog vhdl/bench/CVS/Repository
i2c verilog vhdl/bench/CVS/Root
i2c verilog vhdl/bench/verilog/
i2c verilog vhdl/bench/verilog/CVS/
i2c verilog vhdl/bench/verilog/CVS/Entries
i2c verilog vhdl/bench/verilog/CVS/Repository
i2c verilog vhdl/bench/verilog/CVS/Root
i2c verilog vhdl/bench/verilog/i2c_slave_model.v
i2c verilog vhdl/bench/verilog/spi_slave_model.v
i2c verilog vhdl/bench/verilog/tst_bench_top.v
i2c verilog vhdl/bench/verilog/wb_master_model.v
i2c verilog vhdl/doc/
i2c verilog vhdl/doc/CVS/
i2c verilog vhdl/doc/CVS/Entries
i2c verilog vhdl/doc/CVS/Repository
i2c verilog vhdl/doc/CVS/Root
i2c verilog vhdl/doc/i2c_specs.pdf
i2c verilog vhdl/doc/src/
i2c verilog vhdl/doc/src/CVS/
i2c verilog vhdl/doc/src/CVS/Entries
i2c verilog vhdl/doc/src/CVS/Repository
i2c verilog vhdl/doc/src/CVS/Root
i2c verilog vhdl/doc/src/I2C_specs.doc
i2c verilog vhdl/documentation/
i2c verilog vhdl/documentation/CVS/
i2c verilog vhdl/documentation/CVS/Entries
i2c verilog vhdl/documentation/CVS/Repository
i2c verilog vhdl/documentation/CVS/Root
i2c verilog vhdl/rtl/
i2c verilog vhdl/rtl/CVS/
i2c verilog vhdl/rtl/CVS/Entries
i2c verilog vhdl/rtl/CVS/Repository
i2c verilog vhdl/rtl/CVS/Root
i2c verilog vhdl/rtl/verilog/
i2c verilog vhdl/rtl/verilog/CVS/
i2c verilog vhdl/rtl/verilog/CVS/Entries
i2c verilog vhdl/rtl/verilog/CVS/Repository
i2c verilog vhdl/rtl/verilog/CVS/Root
i2c verilog vhdl/rtl/verilog/i2c_master_bit_ctrl.v
i2c verilog vhdl/rtl/verilog/i2c_master_byte_ctrl.v
i2c verilog vhdl/rtl/verilog/i2c_master_defines.v
i2c verilog vhdl/rtl/verilog/i2c_master_top.v
i2c verilog vhdl/rtl/verilog/timescale.v
i2c verilog vhdl/rtl/vhdl/
i2c verilog vhdl/rtl/vhdl/CVS/
i2c verilog vhdl/rtl/vhdl/CVS/Entries
i2c verilog vhdl/rtl/vhdl/CVS/Repository
i2c verilog vhdl/rtl/vhdl/CVS/Root
i2c verilog vhdl/rtl/vhdl/I2C.VHD
i2c verilog vhdl/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c verilog vhdl/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c verilog vhdl/rtl/vhdl/i2c_master_top.vhd
i2c verilog vhdl/rtl/vhdl/readme
i2c verilog vhdl/rtl/vhdl/tst_ds1621.vhd
i2c verilog vhdl/sim/
i2c verilog vhdl/sim/CVS/
i2c verilog vhdl/sim/CVS/Entries
i2c verilog vhdl/sim/CVS/Repository
i2c verilog vhdl/sim/CVS/Root
i2c verilog vhdl/sim/i2c_verilog/
i2c verilog vhdl/sim/i2c_verilog/CVS/
i2c verilog vhdl/sim/i2c_verilog/CVS/Entries
i2c verilog vhdl/sim/i2c_verilog/CVS/Repository
i2c verilog vhdl/sim/i2c_verilog/CVS/Root
i2c verilog vhdl/sim/i2c_verilog/run/
i2c verilog vhdl/sim/i2c_verilog/run/CVS/
i2c verilog vhdl/sim/i2c_verilog/run/CVS/Entries
i2c verilog vhdl/sim/i2c_verilog/run/CVS/Repository
i2c verilog vhdl/sim/i2c_verilog/run/CVS/Root
i2c verilog vhdl/sim/i2c_verilog/run/INCA_libs/
i2c verilog vhdl/sim/i2c_verilog/run/INCA_libs/CVS/
i2c verilog vhdl/sim/i2c_verilog/run/INCA_libs/CVS/Entries
i2c verilog vhdl/sim/i2c_verilog/run/INCA_libs/CVS/Repository
i2c verilog vhdl/sim/i2c_verilog/run/INCA_libs/CVS/Root
i2c verilog vhdl/sim/i2c_verilog/run/bench.vcd
i2c verilog vhdl/sim/i2c_verilog/run/ncverilog.key
i2c verilog vhdl/sim/i2c_verilog/run/ncverilog.log
i2c verilog vhdl/sim/i2c_verilog/run/run
i2c verilog vhdl/sim/i2c_verilog/run/waves/
i2c verilog vhdl/sim/i2c_verilog/run/waves/CVS/
i2c verilog vhdl/sim/i2c_verilog/run/waves/CVS/Entries
i2c verilog vhdl/sim/i2c_verilog/run/waves/CVS/Repository
i2c verilog vhdl/sim/i2c_verilog/run/waves/CVS/Root
i2c verilog vhdl/software/
i2c verilog vhdl/software/CVS/
i2c verilog vhdl/software/CVS/Entries
i2c verilog vhdl/software/CVS/Repository
i2c verilog vhdl/software/CVS/Root
i2c verilog vhdl/software/drivers/
i2c verilog vhdl/software/drivers/CVS/
i2c verilog vhdl/software/drivers/CVS/Entries
i2c verilog vhdl/software/drivers/CVS/Repository
i2c verilog vhdl/software/drivers/CVS/Root
i2c verilog vhdl/software/include/
i2c verilog vhdl/software/include/CVS/
i2c verilog vhdl/software/include/CVS/Entries
i2c verilog vhdl/software/include/CVS/Repository
i2c verilog vhdl/software/include/CVS/Root
i2c verilog vhdl/software/include/oc_i2c_master.h
i2c verilog vhdl/verilog/
i2c verilog vhdl/verilog/CVS/
i2c verilog vhdl/verilog/CVS/Entries
i2c verilog vhdl/verilog/CVS/Repository
i2c verilog vhdl/verilog/CVS/Root
i2c verilog vhdl/vhdl/
i2c verilog vhdl/vhdl/CVS/
i2c verilog vhdl/vhdl/CVS/Entries
i2c verilog vhdl/vhdl/CVS/Repository
i2c verilog vhdl/vhdl/CVS/Root

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